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A Novel FPGA Architecture of a 2-D Wavelet Transform 二维小波变换的一种新型FPGA结构
Journal of VLSI signal processing systems for signal, image, and video technology Pub Date : 2006-03-01 DOI: 10.1007/s11265-006-4188-y
R. Colom-Palero, R. G. Gironés, A. Sebastià-Cortés
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引用次数: 26
VHDL Implementation of the Fast Wavelet Transform 快速小波变换的VHDL实现
Journal of VLSI signal processing systems for signal, image, and video technology Pub Date : 2006-03-01 DOI: 10.1007/s11265-006-4183-3
P. Salama, M. Rizkalla, M. Eckbauer
{"title":"VHDL Implementation of the Fast Wavelet Transform","authors":"P. Salama, M. Rizkalla, M. Eckbauer","doi":"10.1007/s11265-006-4183-3","DOIUrl":"https://doi.org/10.1007/s11265-006-4183-3","url":null,"abstract":"","PeriodicalId":88019,"journal":{"name":"Journal of VLSI signal processing systems for signal, image, and video technology","volume":"9 1","pages":"223-239"},"PeriodicalIF":0.0,"publicationDate":"2006-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82781616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Survey on Lifting-based Discrete Wavelet Transform Architectures 基于提升的离散小波变换体系研究
Journal of VLSI signal processing systems for signal, image, and video technology Pub Date : 2006-03-01 DOI: 10.1007/s11266-006-4191-3
T. Acharya, C. Chakrabarti
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引用次数: 151
Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication 操作数修改和乘法的倒数和倒数平方根单位
Journal of VLSI signal processing systems for signal, image, and video technology Pub Date : 2006-03-01 DOI: 10.1007/s11265-006-4186-0
K. Wires, M. Schulte
{"title":"Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication","authors":"K. Wires, M. Schulte","doi":"10.1007/s11265-006-4186-0","DOIUrl":"https://doi.org/10.1007/s11265-006-4186-0","url":null,"abstract":"","PeriodicalId":88019,"journal":{"name":"Journal of VLSI signal processing systems for signal, image, and video technology","volume":"05 1","pages":"257-272"},"PeriodicalIF":0.0,"publicationDate":"2006-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88228297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper 10千兆以太网的交错网格编码调制和解码器优化
Journal of VLSI signal processing systems for signal, image, and video technology Pub Date : 2006-03-01 DOI: 10.1007/s11265-006-4182-1
Yongru Gu, K. Parhi
{"title":"Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper","authors":"Yongru Gu, K. Parhi","doi":"10.1007/s11265-006-4182-1","DOIUrl":"https://doi.org/10.1007/s11265-006-4182-1","url":null,"abstract":"","PeriodicalId":88019,"journal":{"name":"Journal of VLSI signal processing systems for signal, image, and video technology","volume":"44 1","pages":"211-221"},"PeriodicalIF":0.0,"publicationDate":"2006-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90478152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results 块匹配运动估计算法及体系结构研究进展
Journal of VLSI signal processing systems for signal, image, and video technology Pub Date : 2006-03-01 DOI: 10.1007/s11265-006-4190-4
Yu-Wen Huang, Ching-Yeh Chen, Chen-Han Tsai, Chun-Fu Shen, Liang-Gee Chen
{"title":"Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results","authors":"Yu-Wen Huang, Ching-Yeh Chen, Chen-Han Tsai, Chun-Fu Shen, Liang-Gee Chen","doi":"10.1007/s11265-006-4190-4","DOIUrl":"https://doi.org/10.1007/s11265-006-4190-4","url":null,"abstract":"","PeriodicalId":88019,"journal":{"name":"Journal of VLSI signal processing systems for signal, image, and video technology","volume":"56 1","pages":"297-320"},"PeriodicalIF":0.0,"publicationDate":"2006-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75556971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 192
Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs 由AOPs生成的伽罗瓦域GF(2m)上正则和正规基乘法器的高效可重构实现
Journal of VLSI signal processing systems for signal, image, and video technology Pub Date : 2006-03-01 DOI: 10.1007/s11266-006-4189-x
J. Imaña, J. M. Sánchez
{"title":"Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs","authors":"J. Imaña, J. M. Sánchez","doi":"10.1007/s11266-006-4189-x","DOIUrl":"https://doi.org/10.1007/s11266-006-4189-x","url":null,"abstract":"","PeriodicalId":88019,"journal":{"name":"Journal of VLSI signal processing systems for signal, image, and video technology","volume":"16 1","pages":"285-296"},"PeriodicalIF":0.0,"publicationDate":"2006-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88223517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems 运动目标分割系统的混合形态学处理单元体系结构
Journal of VLSI signal processing systems for signal, image, and video technology Pub Date : 2006-03-01 DOI: 10.1007/s11265-006-4185-1
Shao-Yi Chien, Bing-Yu Hsieh, Yu-Wen Huang, Shyh-Yih Ma, Liang-Gee Chen
{"title":"Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems","authors":"Shao-Yi Chien, Bing-Yu Hsieh, Yu-Wen Huang, Shyh-Yih Ma, Liang-Gee Chen","doi":"10.1007/s11265-006-4185-1","DOIUrl":"https://doi.org/10.1007/s11265-006-4185-1","url":null,"abstract":"","PeriodicalId":88019,"journal":{"name":"Journal of VLSI signal processing systems for signal, image, and video technology","volume":"33 1","pages":"241-255"},"PeriodicalIF":0.0,"publicationDate":"2006-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85015807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding 加权位集编码下所有混合冗余表示的有效通用加法方案
Journal of VLSI signal processing systems for signal, image, and video technology Pub Date : 2006-02-01 DOI: 10.1007/s11265-005-4177-6
G. Jaberipur, B. Parhami, M. Ghodsi
{"title":"An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding","authors":"G. Jaberipur, B. Parhami, M. Ghodsi","doi":"10.1007/s11265-005-4177-6","DOIUrl":"https://doi.org/10.1007/s11265-005-4177-6","url":null,"abstract":"","PeriodicalId":88019,"journal":{"name":"Journal of VLSI signal processing systems for signal, image, and video technology","volume":"33 2-3 1","pages":"149-158"},"PeriodicalIF":0.0,"publicationDate":"2006-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77915473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
G729 Voice Decoder Design G729语音解码器设计
Journal of VLSI signal processing systems for signal, image, and video technology Pub Date : 2006-02-01 DOI: 10.1007/s11265-005-4180-y
F. Sayadi, E. Casseau, Mohamed Atri, M. Marzougui, R. Tourki, E. Martin
{"title":"G729 Voice Decoder Design","authors":"F. Sayadi, E. Casseau, Mohamed Atri, M. Marzougui, R. Tourki, E. Martin","doi":"10.1007/s11265-005-4180-y","DOIUrl":"https://doi.org/10.1007/s11265-005-4180-y","url":null,"abstract":"","PeriodicalId":88019,"journal":{"name":"Journal of VLSI signal processing systems for signal, image, and video technology","volume":"89 1","pages":"173-184"},"PeriodicalIF":0.0,"publicationDate":"2006-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77040173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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