Advances in Electrical and Electronic Engineering最新文献_第9页

Performance Analysis of the Slip Power Recovery Induction Motor Drive System Under Unbalance Supply Voltages 转差功率回收异步电动机驱动系统在电源电压不平衡情况下的性能分析

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Advances in Electrical and Electronic Engineering Pub Date : 2021-09-28 DOI: 10.15598/aeee.v19i3.4050

Hilmi F. Ameen, Fadhil T. Aula

引用次数: 0

Parameter Estimation of LFM Signal in Low Signal-to-Noise Ratio Using Cross-Correlation Function 基于互相关函数的低信噪比线性调频信号参数估计

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Advances in Electrical and Electronic Engineering Pub Date : 2021-09-28 DOI: 10.15598/aeee.v19i3.4071

M. Duong, J. Veselý, P. Hubáček, P. Janu, Phan Nhat Giang

引用次数: 5

Adjustable Gain Enhanced Fuzzy Logic Controller for Optimal Wheel Slip Ratio Tracking in Hard Braking Control System 可调增益增强模糊控制器在硬制动控制系统中的最优滑移率跟踪

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Advances in Electrical and Electronic Engineering Pub Date : 2021-09-28 DOI: 10.15598/aeee.v19i3.4124

P. C. Eze, Bonaventure Onyekachi Ekengwu, N. Asiegbu, ThankGod I. Ozue

{"title":"Adjustable Gain Enhanced Fuzzy Logic Controller for Optimal Wheel Slip Ratio Tracking in Hard Braking Control System","authors":"P. C. Eze, Bonaventure Onyekachi Ekengwu, N. Asiegbu, ThankGod I. Ozue","doi":"10.15598/aeee.v19i3.4124","DOIUrl":"https://doi.org/10.15598/aeee.v19i3.4124","url":null,"abstract":"This paper has presented hard braking control system based on Adjustable Gain Enhanced Fuzzy Logic Controller (AGE-FLC) for optimal wheel slip ratio tracking performance. The purpose of the study was to improve slip ratio tracking and eliminate cycling while achieving very much shortened distance during emergency braking. The model of a braking vehicle at speed of 30 m.s^-1 subject to wheel locking was developed and implemented in MATLAB/Simulink environment. Simulation was conducted without a controller to study the slip ratio performance of the system on different road surfaces. The simulation results showed that stopping distance was 135.2 m in 5 seconds. A Fuzzy Logic Controller (FLC) whose control signal was enhanced by adding an adjustable gain mechanism to its output was designed. Simulation results showed that the AGE-FLC controller offered optimal tracking of desired wheel slip ratio of 0.1 as fast as possible on all road surface scenarios, while improving the stopping distance by 70.4% on dry road surface, 63.3% on wet road surface, 57.5% on cobblestone road surface and 48.8% on snow road surface in 2.651seconds.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":" ","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47895281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploiting Full-duplex and Fixed Power Allocation Approaches for Dual-hop Transmission in Downlink NOMA 利用全双工和固定功率分配方法实现下行NOMA中的双跳传输

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Advances in Electrical and Electronic Engineering Pub Date : 2021-09-28 DOI: 10.15598/aeee.v19i3.4116

T. Nguyen, D. Do

引用次数: 1

Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier 摊位编码的Karatsuba:一种新型的硬件效率乘法器

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Advances in Electrical and Electronic Engineering Pub Date : 2021-09-28 DOI: 10.15598/AEEE.V19I3.4199

Riya Jain, Khushbu Pahwa, N. Pandey

{"title":"Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier","authors":"Riya Jain, Khushbu Pahwa, N. Pandey","doi":"10.15598/AEEE.V19I3.4199","DOIUrl":"https://doi.org/10.15598/AEEE.V19I3.4199","url":null,"abstract":"There is a recent boom being witnessed in emerging areas like IoMT (Internet of Medical Things), Artificial Intelligence for healthcare, and disaster management. These novel research frontiers are critical in terms of hardware and cannot afford to compromise accuracy or reliability. Multiplier, being one of the most heavily used components, becomes crucial in these applications. If optimized, multipliers can impact the overall performance of the system. Thus, in this paper, an attempt has been made to determine the potential of accurate multipliers while meeting minimal hardware requirements. In this paper, we propose a novel Booth-Encoded Karatsuba multiplier and provide its comparison with a Booth-Encoded Wallace tree multiplier. These architectures have been developed using two types of Booth encoding: Radix-4 and Radix-8 for 16-bit, 32-bit and 64-bit multiplications. The algorithm is designed to be parameterizable to different bit widths, thereby offering higher flexibility. The proposed mul- tiplier offers advantage of enhanced performance with significant reduction in hardware while negligibly trad- ing off the Power Delay Product (PDP). It has been observed that the performance of the proposed architecture increases with increasing multiplier size due to significant reduction in hardware and slight increase in PDP. All the architectures have been implemented in Verilog HDL using Xilinx Vivado Design Suite.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":"19 1","pages":"272-281"},"PeriodicalIF":0.6,"publicationDate":"2021-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46134466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and Implementation of Parallel Bypass Bin Processing for CABAC Encoder CABAC编码器并行旁路Bin处理的设计与实现

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Advances in Electrical and Electronic Engineering Pub Date : 2021-09-28 DOI: 10.15598/aeee.v19i3.4010

Nagaraju Mamidi, S. Gupta, Vijaya Bhadauria

{"title":"Design and Implementation of Parallel Bypass Bin Processing for CABAC Encoder","authors":"Nagaraju Mamidi, S. Gupta, Vijaya Bhadauria","doi":"10.15598/aeee.v19i3.4010","DOIUrl":"https://doi.org/10.15598/aeee.v19i3.4010","url":null,"abstract":"The ever-increasing demand for high-quality digital video requires efficient compression techniques and fast video codecs. It necessitates increased complexity of the video codec algorithms. So, there is a need for hardware accelerators to implement such complex algorithms. The latest video compression algorithms such as High-Efficiency Video Coding (HEVC) and Versatile Video Coding (VVC) have been adopted Context-based Adaptive Binary Arithmetic Coding (CABAC) as the entropy coding method. The CABAC has two main data processing paths: regular and bypass bin path, which can achieve good compression when used with Syntax Elements (SEs) statistics. However, it is highly intrinsic data dependence and has sequential coding characteristics. Thus, it is challenging to parallelize. In this work, a 6-core bypass bin path having high-throughput and low hardware area has been proposed. It is a parallel architecture capable of processing up to 6 bypass bins per clock cycle to improve throughput. Further, the resource-sharing techniques within the binarization and a common controller block have reduced the hardware area. The proposed architecture has been simulated, synthesized, and prototyped on 28 nm Artix 7 Field Programmable Gate Array (FPGA). The implementation of Application Specific Integrated Circuit (ASIC) has been done using 65 nm CMOS technology. The proposed design achieved a throughput of 1.26 Gbin/s at 210 MHz operating frequency with a low hardware area compared to existing architectures. This architecture also supports multi-standard (HEVC/VVC) encoders for Ultra High Definition (UHD) applications.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":" ","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47693994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Typical Values of Energy Performance Indicators in Road Lighting 道路照明中能源性能指标的典型值

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Advances in Electrical and Electronic Engineering Pub Date : 2021-06-30 DOI: 10.15598/AEEE.V19I2.4149

D. Gašparovský, P. Janiga, J. Raditschová

引用次数: 2

The Validation of Various Technological Factors Impact on the Electron Beam Lithography Process 影响电子束光刻工艺的各种工艺因素的验证

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Advances in Electrical and Electronic Engineering Pub Date : 2021-06-30 DOI: 10.15598/aeee.v19i2.4133

A. Zawadzka, Kornelia Indykiewic, R. Paszkiewicz

{"title":"The Validation of Various Technological Factors Impact on the Electron Beam Lithography Process","authors":"A. Zawadzka, Kornelia Indykiewic, R. Paszkiewicz","doi":"10.15598/aeee.v19i2.4133","DOIUrl":"https://doi.org/10.15598/aeee.v19i2.4133","url":null,"abstract":"One of the most significant processes in micro- and nanoelectronics technology is Electron Beam Lithography (EBL). This technique maintains a leading role in extremely high-resolution structures fabrication process with micro- and nanometer dimensions down to dozens of nanometers. The EBL is a highly complex process and determining fundamental technological factors that affect the final pattern shape is crucial. One of them is the used lithography system, consisting of a substrate and a polymer layer that affects the electron scattering effects. To obtain the required pattern geometry, it is also necessary to properly select the electron beam parameters for given materials. The aim of this work is to discuss the differences in the exposition process for various accelerating voltage (EHT) values. Additionally, the investigation of geometry features and the impact of the exposure dose and the structure dimensions on the final absorbed energy distribution profile in the resist layer is presented and discussed. Numerical studies, using CASINO software and Monte Carlo method, are presented to compare the energy distribution in the polymer that affects the structure formation in the resist layer.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":" ","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44918896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Energy Storage Technology and Converter Topology for Primary Frequency Control in Thermal Power Plant 火电厂一次变频调速的储能技术与变换器拓扑

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Advances in Electrical and Electronic Engineering Pub Date : 2021-06-30 DOI: 10.15598/AEEE.V19I2.3945

M. Vins, J. Dragoun, Martin Sirový

引用次数: 1

Silicon Resistivity Behaviour 硅电阻率行为

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Advances in Electrical and Electronic Engineering Pub Date : 2021-06-30 DOI: 10.15598/AEEE.V19I2.4140

G. Cibira

引用次数: 0