2017 IEEE 67th Electronic Components and Technology Conference (ECTC)最新文献_第3页

Enhanced Thermal Conductivity of the Underfill Materials Using Insulated Core/shell Filler Particles for High Performance Flip Chip Applications 在高性能倒装芯片应用中使用绝缘芯/壳填料颗粒增强下填充材料的导热性

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.196

Tae-Ryong Kim, Kisu Joo, B. Lim, Sung-Soon Choi, B. Lee, E. Yoon, Se Young Jeong, M. Yim

{"title":"Enhanced Thermal Conductivity of the Underfill Materials Using Insulated Core/shell Filler Particles for High Performance Flip Chip Applications","authors":"Tae-Ryong Kim, Kisu Joo, B. Lim, Sung-Soon Choi, B. Lee, E. Yoon, Se Young Jeong, M. Yim","doi":"10.1109/ECTC.2017.196","DOIUrl":"https://doi.org/10.1109/ECTC.2017.196","url":null,"abstract":"In this study, we investigated the correlation between thermal conductivity and insulative shell thickness of SiO2 coated Ag (SCA) particles for the thermal filler material in the high performance underfill with focus on improved thermal conductivity. We synthesized the coating of various SiO2 insulation layer on the surface of spherical Ag powder and used them for underfill material formulation to achieve >2 W/mK grade high thermal conductivity capillary underfill. In order to achieve powder distribution with gaussian curve additional spherical alumina was mixed with SCA powder. This mixture blended with epoxy based multifunctional resin matrix. Trend profiling of thermal conductivity and electrical resistivity as a function of SiO2 shell thickness were performed. In addition, correlation of thermal conductivity and viscosity were investigated. Resulting capillary underfill with SCA powders showed 2.14 W/mK thermal conductivity and passed thermal cycling test corresponding to JEDEC LEVEL 3.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"84 1","pages":"1340-1347"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77142541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Design of Miura Folding-Based Micro-Supercapacitors as Foldable and Miniaturized Energy Storage Devices 基于Miura折叠的微型超级电容器可折叠和小型化储能装置的设计

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.150

B. Song, Yun Chen, K. Moon, C. Wong

引用次数: 4

Package-Level Si Micro-Fluid Cooler with Enhanced Jet Array for High Performance 3D Systems 包级硅微流体冷却器与增强的射流阵列高性能3D系统

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.42

Yong Han, B. L. Lau, G. Tang, Seow Meng Low, J. Goh

引用次数: 1

Low Pressure Solid-State Bonding Using Silver Preforms for High Power Device Packaging 大功率器件封装用银预制体低压固态键合

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.192

Jiaqi Wu, Chin C. Lee

{"title":"Low Pressure Solid-State Bonding Using Silver Preforms for High Power Device Packaging","authors":"Jiaqi Wu, Chin C. Lee","doi":"10.1109/ECTC.2017.192","DOIUrl":"https://doi.org/10.1109/ECTC.2017.192","url":null,"abstract":"Silver (Ag) has been emerging as an attractive die-attach material for high power devices because of its highest thermal conductivity among metals and high melting stability. The most well-known silver die-attach technique is to sinter micro-or nano-silver pastes. The challenging issues of sintered Ag joints are pores in the joint and migration of unfriendly species such as chlorine ions through these pores. In this paper, a novel Ag die-attach technique using foils is reported. The foils are fabricated in house using many runs of cold rolling and subsequent annealing. Annealing is needed to establish favorable microstructure. X-ray diffraction (XRD) is carried out to reveal the crystallographic information. Solid-state bonding is conducted in 0.1 torr vacuum at 300 °C assisted by low applied pressure (1,000 psi). This pressure is several orders of magnitude lower than what used in conventional thermal compression bonding. The Si/Ag/Cu structure, where Ag is the foil, is bonded in one step to achieve two bonding interfaces. Prior to bonding, Si is metallized with thin Cr and Au layers. Cross section SEM images show that there are no large voids and cracks in the interfacial regions. The Ag region is a dense pure silver layer without any foreign substances. Regardless of significant coefficient of thermal expansion (CTE) mismatch between silicon and copper, the bonded samples do not crack after cooling down to room temperature. This indicates that the ductile Ag layer is able to manage the stress produced by the CTE mismatch. The new Ag die-attach method produces joints of lowest possible thermal resistance and extremely high operation temperature. It should be very valuable to high power and high temperature electronics and photonics.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"2002-2007"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88213507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Temperature Ultrasonic Bonding of Cu/Sn Microbumps with Au Layer for High Density Interconnection Applications Cu/Sn微凸点与Au层的低温超声键合用于高密度互连

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.217

Qinghua Zeng, Y. Guan, J. Chen, Yufeng Jin

{"title":"Low-Temperature Ultrasonic Bonding of Cu/Sn Microbumps with Au Layer for High Density Interconnection Applications","authors":"Qinghua Zeng, Y. Guan, J. Chen, Yufeng Jin","doi":"10.1109/ECTC.2017.217","DOIUrl":"https://doi.org/10.1109/ECTC.2017.217","url":null,"abstract":"Flip-chip bonding has become an efficient method to realize fine-pitch interconnection in high density interconnection applications. Thermal-compression bonding of Cu/Sn microbumps can induce extra thermal stress because of high bonding temperature, long bonding time and high bonding force. Temperature, time and force are expected to be decreased to improve the thermal-mechanical reliability of the integration systems. In this work, low-temperature ultrasonic bonding of Cu/Sn microbumps with a thin layer of gold was studied. We also studied bonding of redistribution layers (RDLs) that consisted of electrodeposited copper and a thin layer of gold. The feasibility of the low-temperature ultrasonic bonding was demonstrated through the preliminary experimental results. Cu/Sn microbumps with Au layer were successfully bonded through a quick bonding process and a followed annealing process. However, in the case of bonding of the RDLs, the cross-section of some bonded RDLs showed that cracks existed at the interface of Au/Au layers, which resulted from the uneven surface. The electrodeposition process needs improving to get a flatter surface and the parameters of the bonding process still needs to be optimized.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"87 1","pages":"1894-1899"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86764511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Highly Efficient and Stable Quantum Dot Light Emitting Diodes Optimized by Micro-Packaged Luminescent Microspheres 微封装发光微球优化的高效稳定量子点发光二极管

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.74

Kai Wang, Xiaobing Luo, Sheng Liu, X. W. Sun

引用次数: 0

Miniaturization of Planar Packaged Inductor Using NiZn and Low Cost Screen Printing Technique 利用NiZn和低成本丝网印刷技术实现平面封装电感的小型化

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.183

C. Pardue, M. Bellaredj, A. Davis, M. Swaminathan

{"title":"Miniaturization of Planar Packaged Inductor Using NiZn and Low Cost Screen Printing Technique","authors":"C. Pardue, M. Bellaredj, A. Davis, M. Swaminathan","doi":"10.1109/ECTC.2017.183","DOIUrl":"https://doi.org/10.1109/ECTC.2017.183","url":null,"abstract":"Given the recent interest in power delivery design for the Internet of Things (IoT), current work aims to design a packaged power delivery solution for IoT. The power inductor takes up a large amount of the area in such an implementation. Planar power inductors are preferred for fabrication simplicity and cost. However, air core inductors do not have sufficient area efficiency for IoT solutions, necessitating the integration of a magnetic core on a planar inductor. This research demonstrates a low cost method of miniaturizing planar inductors using stencil printing technique with a magnetic composite for embedded power inductors for IoT edge device applications. Planar spiral inductors of varying dimensions and inductances are designed using a full wave EM solver. Inductors are then fabricated on FR4 using standard printed wiring board process. NiZn is a low loss magnetic material and is mixed with an epoxy and solvent to facilitate stencil printing. Stencil printing is a low cost fabrication method with great utility to electronic packaging. A single layer of NiZn is screen printed as squares directly on the fabricated spiral inductors. Measurements are performed using a vector network analyzer at frequencies between 10 and 50 MHz. The measured inductance of the inductors ranges from 37 nH-340 nH without NiZn to 42 nH-452 nH with a single NiZn layer at the operating frequencies. In addition, the Q factor is actually improved at the frequency of operation, as the inductance gained from the magnetic layer is more significant than the loss incurred. This increase in inductance leads to great potential for decrease of size of packaged inductors.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"3 1","pages":"2275-2281"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83503387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Expanding Film and Process for High Efficiency 5 Sides Protection and FO-WLP Fabrication 高效五面保护和FO-WLP制造的膨胀膜及工艺

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.293

K. Honda, N. Suzuki, T. Nonaka, H. Noma, Yoshinobu Ozaki

引用次数: 5

Mechanical Characterization of Anodic Bonding Using Chevron Microchannel 用Chevron微通道表征阳极键合的力学特性

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.335

David C. Woodrum, M. Nasr, Xuchen Zhang, M. Bakir, S. Sitaraman

{"title":"Mechanical Characterization of Anodic Bonding Using Chevron Microchannel","authors":"David C. Woodrum, M. Nasr, Xuchen Zhang, M. Bakir, S. Sitaraman","doi":"10.1109/ECTC.2017.335","DOIUrl":"https://doi.org/10.1109/ECTC.2017.335","url":null,"abstract":"As power demands for microelectronic devices continue to rise, new techniques for heat dissipation require innovative fabrication solutions such as on-chip cooling methods. The mechanical reliability of these high-powered, high-pressure systems is particularly sensitive to the interfacial strengths within the microelectronic architectures. In research at Georgia Tech, on-chip cooling methodologies involve cooling of devices with high-pressure coolant which is pumped through a microchannel. The microchannels are etched directly into a silicon wafer and then capped by a second wafer of pyrex glass. When fluid flows through the system, internal pressures can exceed 2000 kPa in certain locations of the microchannel. Overall system failure due to cracking of the brittle materials is of particular interest given the potential for catastrophic crack propagation. Using a combination of experiments and modeling, a methodology for predicting interfacial and cohesive strength of the silicon-glass bonded microchannel system has been developed. The objective of this work is to demonstrate the results of the experimental test technique and to extract appropriate silicon-glass interfacial test data in conjunction with numerical modeling of the fracture conditions.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"1646-1653"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89379936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Very High-Dense on-Board Optical Module Realizing >1.3 Tb/s/Inch ^2 实现>1.3 Tb/s/Inch ^2的超高密度板载光模块

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.213

K. Nagashima, T. Uemura, A. Izawa, Y. Ishikawa, H. Nasu

引用次数: 4