2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)最新文献_第10页

FPGA based area optimized parallel pipelined radix-22 feed forward FFT architecture 基于FPGA的区域优化并行流水线基数-22前馈FFT结构

2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2016-05-20 DOI: 10.1109/RTEICT.2016.7808042

S. Ajmal, S. Gangadharaiah

引用次数: 6

Computer aided detection of abnormal red blood cells 计算机辅助检测异常红细胞

2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2016-05-20 DOI: 10.1109/RTEICT.2016.7808132

Pooja Tukaram Dalvi, Nagaraj Vernekar

引用次数: 19

Multi-object tracking using TLD framework 基于TLD框架的多目标跟踪

2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2016-05-20 DOI: 10.1109/RTEICT.2016.7808137

S. Sharma, A. Khachane, Dilip Motwani

引用次数: 5

Volume measurement of object using computer vision 用计算机视觉测量物体体积

2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2016-05-20 DOI: 10.1109/RTEICT.2016.7808143

Tushar Jadhav, Santosh M. Kamble

引用次数: 4

Symmetric color image encryption algorithm using fractional DRPM and chaotic baker map 基于分数阶DRPM和混沌baker映射的对称彩色图像加密算法

2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2016-05-20 DOI: 10.1109/RTEICT.2016.7808152

R. Jain, J. B. Sharma

{"title":"Symmetric color image encryption algorithm using fractional DRPM and chaotic baker map","authors":"R. Jain, J. B. Sharma","doi":"10.1109/RTEICT.2016.7808152","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7808152","url":null,"abstract":"Security of image data is essential during communication from various security attacks. This paper proposed a new technique for RGB color image encryption and decryption by the combination of shuffling and masking. The chaotic Baker map is used for first layer of image encryption by randomizing the pixels of each components of color image such as red, green and blue and then applying the diffusion process i.e. fractional dual random phase masks (FDRPM) technique which is applied on each component to increase the security level of given method. The order of Discrete Fractional Fourier Transform (DFRFT) act as a key for the process which provides extra degree of security to the proposed system. Matlab simulations are performed to check the security robustness of proposed scheme. Performance of proposed scheme is verified by noise analysis such as mean square error (MSE) and various differential analysis such as Unified Average Change Intensity (UACI) and Number of Pixels Change Rate (NPCR). Results of various analysis shows that the novel proposed encryption technique shows high efficiency and security for color images.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"1 1","pages":"1835-1840"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90244719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Exploring split ring resonators for GHz applications 探索用于GHz应用的分环谐振器

2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2016-05-20 DOI: 10.1109/RTEICT.2016.7807884

S. Rosaline, S. Raghavan

引用次数: 1

Analysis and design of reversible excess-3 adder and subtractor 可逆超3加减法器的分析与设计

2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2016-05-20 DOI: 10.1109/RTEICT.2016.7807849

V. S. P. Nayak, N. Ramchander, R. Reddy, Tapas Marandi

{"title":"Analysis and design of reversible excess-3 adder and subtractor","authors":"V. S. P. Nayak, N. Ramchander, R. Reddy, Tapas Marandi","doi":"10.1109/RTEICT.2016.7807849","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807849","url":null,"abstract":"Power is one of the most important design parameter after speed, in integrated circuit. One of the basic fundamental component in such circuit is adder and subtractor. In order to optimize such circuits there is need of designing efficient and low power fundamental blocks. As per the Launder's principle, KTln2 heat is dissipated if there is any loss in bit. Excess-3 code is one of the sequential codes used widely in digital circuits for performing arithmetic operations. Since conventional excess-3 adder and excess-3 subtractor both circuits designed in irreversible logic observe large amount of leakage power. By keeping this as main point, this paper explains the process of designing 4-bit excess-3 adder and subtactor in 90nm technology and also worked to combine both individual circuits to design as a single circuit where it can perform addition and subtraction on excess-3 coded bits simultaneously. This paper also gives mathematical analysis of n-bit proposed circuit in terms of number of gates, quantum cost, garbage output, power and delay. Finally simulation results are obtained by using cadence virtuoso and observed power dissipation for proposed circuit is 221uWIn this paper detail simulation results along with the power graph submitted.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"10 1","pages":"397-400"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88652959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analysis of duo-binary modulation scheme in single channel on the basis of BER 基于误码率的单信道双二进制调制方案分析

2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2016-05-20 DOI: 10.1109/RTEICT.2016.7807778

Urvashi Jadon, Hiroshama Nain, V. Mishra

引用次数: 1

Cluster based routing protocol to prolong network lifetime through mobile sink in WSN 无线传感器网络中基于集群的路由协议，利用移动接收器延长网络生存期

2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2016-05-01 DOI: 10.1109/RTEICT.2016.7808039

B. Y. Kushal, M. Chitra

引用次数: 29

Design of low power operational amplifier and digital latch circuits using power efficient charge steering technique 低功率运算放大器和数字锁存电路的设计

2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2016-05-01 DOI: 10.1109/RTEICT.2016.7807834

Raju Ranjan

{"title":"Design of low power operational amplifier and digital latch circuits using power efficient charge steering technique","authors":"Raju Ranjan","doi":"10.1109/RTEICT.2016.7807834","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807834","url":null,"abstract":"In today's world power consumption is a burning issue. Research is going on to find out various new power efficient design techniques. Power dissipation could be reduced by transforming continuous-time current-steering circuits into discrete-time charge-steering circuits. Charge steering shows all potential to emerge as an effective technique to reduce power dissipation for high-speed circuits. This technique can be exploited in the design of both analog and semi-analog circuits such as an op-amp, latches and clock-data recovery (CDR) circuits. This paper discusses the design techniques of charge steering circuits like op-amp and latches. Both 1st stage and 2nd stage op-amp circuits and different type of latches in a single stage and cascade forms are designed. The power and performances of the charge steering circuits are also compared with conventional design techniques like current mode logic (CML) circuits to show the improvements. The results show that the op-amp power dissipation is reduced by approximately 87% with better gain. All circuits have been designed using UMC's 180 nm CMOS technology.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"14 1","pages":"316-321"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74505717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1