2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)最新文献_第6页

A comparison of cost construction methods onto a C6678 platform for stereo matching C6678平台立体匹配成本构建方法的比较

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853821

Judicael Menant, G. Gautier, J. Nezan, M. Pressigout, L. Morin

引用次数: 1

ARM-FPGA based platform for automated adaptive wireless communication systems using partial reconfiguration technique 基于ARM-FPGA的自动化自适应无线通信系统平台，采用部分重构技术

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853806

Mohamad-Al-Fadl Rihani, Jean-Christophe Prévotet, F. Nouvel, M. Mroué, Y. Mohanna

{"title":"ARM-FPGA based platform for automated adaptive wireless communication systems using partial reconfiguration technique","authors":"Mohamad-Al-Fadl Rihani, Jean-Christophe Prévotet, F. Nouvel, M. Mroué, Y. Mohanna","doi":"10.1109/DASIP.2016.7853806","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853806","url":null,"abstract":"Recent fixed and mobile wireless communication systems have attracted researchers to propose new techniques and methodologies that greatly improve performance. For example, adaptive techniques have improved the wireless channel efficiency while decreasing the overall power consumption. They consist in reconfiguring parts of the global system automatically according to different parameters. In parallel, circuit technology has also considerably evolved. One example is Field Programmable Gate Arrays (FPGAs) that are now suitable for implementing the physical layer of most complex wireless communication systems. This has been made possible thanks to their high level of performance, flexibility, and bit-level programming. In these devices, the Dynamic Partial Reconfiguration (DPR) constitutes a well known technique for reconfiguring only a specific area within the circuit. This technique offers efficient resource utilization, reduced power consumption and permits the optimization of the configuration time. In our work, we benefit from this technology to implement a wireless communication system in hardware. Hardware reconfiguration is performed automatically according to adaptive decision processes running on top of a micro-kernel that manages partial reconfiguration. The system is implemented on a ZedBoard which features a Xilinx Zynq 7000 System on Chip (SoC).","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"6 1","pages":"113-120"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72734039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Custom processor design for efficient, yet flexible Lucas-Kanade optical flow 定制处理器设计，高效，灵活的卢卡斯-卡纳德光流

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853810

S. Smets, T. Goedemé, M. Verhelst

{"title":"Custom processor design for efficient, yet flexible Lucas-Kanade optical flow","authors":"S. Smets, T. Goedemé, M. Verhelst","doi":"10.1109/DASIP.2016.7853810","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853810","url":null,"abstract":"State-of-the-art solutions to optical flow fail to jointly offer high density flow estimation, low power consumption and real time operation, rendering them unsuitable for embedded applications. Joint hardware-software scalability at run-time is crucial to achieve these conflicting requirements in one device. This paper therefore presents a scalable Lucas-Kanade optical flow algorithm, together with a flexible power-optimized processor architecture. The C-programmable processor exploits algorithmic scalability through innovations in its memory structure, memory interface, and datapath optimized for efficient convolutions. Jointly, the scalable flow algorithm and optimized computer vision hardware platform enable applications to on-the-fly trade-off throughput and power consumption in function of flow density and accuracy. The processor chip is synthesized in 40nm CMOS technology and verified on FPGA. The architecture is capable of scaling the frame rate at run-time and processes 16fps of dense optical flow at 640×480 resolution with 15.06° average angular error, while only consuming 24mW.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"54 1","pages":"138-145"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74993099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

FPGA-based Hardware-in-the-Loop environment using video injection concept for camera-based systems in automotive applications 基于fpga的环内硬件环境，使用视频注入概念，用于汽车应用中基于摄像头的系统

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853817

M. Komorkiewicz, Krzysztof Turek, P. Skruch, T. Kryjak, M. Gorgon

引用次数: 11

Demo: Reconfigurable Platform Composer Tool 演示:可重构平台编写工具

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853835

Carlo Sau, Tiziana Fanni, P. Meloni, L. Raffo, M. Pelcat, F. Palumbo

引用次数: 0

Special session 2 Computer vision and Image analysis 特别会议2计算机视觉和图像分析

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853819

P. Delmas, R. Ababou

引用次数: 0

ELM-based hyperspectral imagery processor for onboard real-time classification 基于elm的机载实时分类高光谱图像处理器

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853795

Koldo Basterretxea, Unai Martinez-Corral, Raul Finker, I. D. Campo

{"title":"ELM-based hyperspectral imagery processor for onboard real-time classification","authors":"Koldo Basterretxea, Unai Martinez-Corral, Raul Finker, I. D. Campo","doi":"10.1109/DASIP.2016.7853795","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853795","url":null,"abstract":"Hyperspectral imagery is being widely used for accurate object detection and terrain feature classification. Modern imaging spectrometers produce huge amounts of data that are compressed onboard and downloaded to ground stations to be processed. Increasing spectral resolution and data acquisition rates demand more efficient compression techniques to meet downlink bandwidth restrictions. A different approach to reducing data-transfer bottlenecks consists of processing hyperspectral imagery information onboard. Real-time onboard processing would, at the same time, broaden the scope of missions that spacecrafts and aircrafts carrying hyperspectral cameras could fulfill by providing them with immediate decision-making capacity in critical circumstances. This paper investigates the use of Extreme Learning Machines (ELMs) for the classification of high dimensional data, and how specialized hardware and application-specific processor design can help to produce high performance, lightweight, and reduced power consumption systems for onboard hyperspectral imagery processing.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"393 1","pages":"43-50"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76454707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Memory management in embedded vision systems: Optimization problems and solution methods 嵌入式视觉系统的记忆管理:优化问题及解决方法

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853820

K. H. Salem, Yann Kieffer, S. Mancini

{"title":"Memory management in embedded vision systems: Optimization problems and solution methods","authors":"K. H. Salem, Yann Kieffer, S. Mancini","doi":"10.1109/DASIP.2016.7853820","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853820","url":null,"abstract":"Embedded vision systems design faces a memory-wall kind of challenge: images are big, and therefore memories containing them have high latency; and still, high performance is desired. For the case of non-linear processings, Mancini and Rousseau (Proc. DATE 2012) have designed a software generator of adhoc memory hierarchies, called Memory Management Optimization (MMOpt). While the performance of the generated circuits is very good, design-time decisions have to be made regarding their operation in order to handle finely the compromise between the usual metrics of design area, energy consumption, and performance. This study tackles the optimization challenge set by the design of the operational behavior of the memory hierarchy generated by MMOpt. After a precise formulation as a 3-objective optimization problem is given, two algorithms are proposed, and their performance is analyzed on real-world processings against the previously proposed algorithms. The results show a reduction of the amount of transferred data by 17% on average, and of the computing times by 11.7%, for the same design area.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"72 1","pages":"200-207"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77377126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Memory efficient Multi-Scale Line Detector architecture for retinal blood vessel segmentation 基于多尺度线性检测器的视网膜血管分割方法

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853797

Hamza Bendaoudi, F. Cheriet, J. Langlois

引用次数: 3

Hardware architecture for lowering the error floor of LTE turbo codes 降低LTE turbo码误码层的硬件结构

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853805

Thibaud Tonnellier, Camille Leroux, B. Gal, C. Jégo, B. Gadat, N. V. Wambeke

引用次数: 2