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2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)最新文献

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Hardware acceleration of Maximum-Likelihood angle estimation for automotive MIMO radars 汽车MIMO雷达最大似然角估计的硬件加速
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853815
F. Meinl, M. Kunert, H. Blume
{"title":"Hardware acceleration of Maximum-Likelihood angle estimation for automotive MIMO radars","authors":"F. Meinl, M. Kunert, H. Blume","doi":"10.1109/DASIP.2016.7853815","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853815","url":null,"abstract":"Direction of arrival (DOA) estimation is an important array signal processing technique, used by various applications such as radar, sonar or wireless communication. Most of the known DOA algorithms suffer from a significant performance reduction and even fail completely under difficult conditions, like small antenna aperture size, correlated signals or a small number of snapshots. Maximum-Likelihood (ML) methods have been investigated thoroughly and are known to still work even in such difficult scenarios. Though, the major drawback of ML methods is their computational cost, especially in the case of large MIMO (multiple-input multiple-output) configurations. This work presents a novel hardware accelerator architecture, which is able to compute the exact ML estimation in the case of one or two targets. It is shown, that the computational demanding vector product can be implemented with the help of CORDIC units, which help to save a considerable amount of hardware resources. Furthermore, the result of the single target estimator can be reused to efficiently compute the estimates in the two-target case. Finally, the performance of the architecture is evaluated by a FPGA implementation which is able to process more than 20 000 detections from 16 channels with 256 steering vectors in real-time (25 Hz).","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"31 1","pages":"168-175"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73328809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Generation of schedule tables on multi-core systems for AUTOSAR applications AUTOSAR应用的多核系统调度表的生成
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853818
Wenhao Wang, Fabrice Camut, Benoît Miramond
{"title":"Generation of schedule tables on multi-core systems for AUTOSAR applications","authors":"Wenhao Wang, Fabrice Camut, Benoît Miramond","doi":"10.1109/DASIP.2016.7853818","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853818","url":null,"abstract":"The recent migration from single-core to multi-core platforms in the automotive domain reveals great challenges for the legacy embedded software design flow. First of all, software designers need new methods to fill the gap between application description and tasks deployment. Secondly, the use of multiple cores has also to remain compatible with real-time and safety design constraints. Finally, developers need tools to assist them in the new steps of the design process. We propose in this paper a method integrated in the AUTOSAR design flow for the generation of schedule tables imposing the execution constraints onto a multi-core architecture. We consider an engine control application described in AUTOSAR as a set of periodic and dependent runnables. For that, we propose a formalization of periodic dependencies adapted to this automotive framework and present a scheduling algorithm taking into account this specificity. We leaded experiments with a complex and real world control application onto automotive multi-core systems. We present our working process enabling the generation of several execution schemes for this industrial application. The results show that our scheduling method benefits the multi-core migration to generate solutions best suited to safety standards by reducing the total jitter.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"25 1","pages":"191-198"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77372451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
FPGA-based bio-inspired architecture for multi-scale attentional vision 基于fpga的多尺度注意力视觉仿生架构
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853828
N. Cuperlier, F.J.Q. deMelo, Benoît Miramond
{"title":"FPGA-based bio-inspired architecture for multi-scale attentional vision","authors":"N. Cuperlier, F.J.Q. deMelo, Benoît Miramond","doi":"10.1109/DASIP.2016.7853828","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853828","url":null,"abstract":"Attention-based bio-inspired vision can be studied as a different way to consider sensor processing, firstly allowing to reduce the amount of data transmitted by connected cameras and secondly advocating a paradigm shift toward neuro-inspired processing for the post-processing of the few regions extracted from the visual field. The computational complexity of the corresponding vision models leads us to follow an in-sensor approach in the context of embedded systems. We propose in this paper an attention-based smart-camera which extracts salient features based on retina receptive fields at multiple scales and in real-time thanks to a dedicated hardware architecture. The results show that the entire visual chain can be embedded into a FPGA-SoC device delivering up to 60 frames per second. The features provided by the smart-camera can then be learned by external neural networks in order to accomplish various applications.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"23 1","pages":"231-232"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72619897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Demo: SLP-aware word length optimization 演示:支持slp的字长优化
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853829
Ali Hassan El Moussawi, Steven Derrien
{"title":"Demo: SLP-aware word length optimization","authors":"Ali Hassan El Moussawi, Steven Derrien","doi":"10.1109/DASIP.2016.7853829","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853829","url":null,"abstract":"Many embedded processors do not support floating-point arithmetic. But they generally provide support for SIMD as a mean to improve performance for near-zero cost overhead. Achieving good performance when targeting such processors requires the use of fixed-point arithmetic and efficient SIMDization. To reduce applications time-to-market, automatic SIMDization and floating-point conversion methodologies have been proposed. In this paper we show that these two problems are strongly related and should be considered jointly. We briefly present a new SLP-aware floating-point conversion flow.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"185 1","pages":"233-234"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80574221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Session 3: Method and tools for system design 第三部分:系统设计的方法和工具
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853799
D. Göhringer
{"title":"Session 3: Method and tools for system design","authors":"D. Göhringer","doi":"10.1109/DASIP.2016.7853799","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853799","url":null,"abstract":"The four papers in this session present novel methodologies covering different aspects of system design. The first paper proposes a decentralized system-level security approach for task isolation on heterogeneous MPSoCs. A first prototype of the isolation unit is presented and realized in VHDL. The second paper focuses on low power design methods for system design based on lightweight dataflow programming techniques. The approach is evaluated by designing an FPGA-based accelerator for a deep neural network. The third paper presents a method for automated code generation for SIMD architectures based on constraint programming. The benefits of the approach are evaluated with DSP kernels and by comparing the results to hand-optimized code. Finally, the fourth paper proposes a methodology based on fuzzy logic for object image quality assessment (IQA) and compares it against other IQA approaches.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"24 1","pages":"73"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82200401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Demo abstract: How fuzzy logic can enhance energy management in Wireless Sensor nodes equipped by energy harvesters and wake-up radios 演示摘要:模糊逻辑如何增强配备能量采集器和唤醒无线电的无线传感器节点的能量管理
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853827
Fayçal Ait Aoudia, M. Gautier, O. Berder
{"title":"Demo abstract: How fuzzy logic can enhance energy management in Wireless Sensor nodes equipped by energy harvesters and wake-up radios","authors":"Fayçal Ait Aoudia, M. Gautier, O. Berder","doi":"10.1109/DASIP.2016.7853827","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853827","url":null,"abstract":"Power management is an important issue in the design of Energy Harvesting Wireless Sensor Networks (EHWSNs). In this kind of networks, each Energy Harvesting Node (EH-node) must dynamically adapt its performance in order to avoid power failures while maintaining a good quality of service. The power management policy is implemented on each node by a Power Manager (PM). In this demonstration, the behaviour of Fuzzyman, a novel PM based on fuzzy control, is introduced. The performance of this PM is also shown in terms of energy budget and throughput for a given protocol. Moreover, the benefit of using emerging wake-up radio technology is also demonstrated.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"53 1","pages":"229-230"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78979170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Demo: MPPA® manycore processor towards future ADAS system solutions 演示:面向未来ADAS系统解决方案的MPPA®多核处理器
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853834
Pierre-Edouard Beaucamps, Frédéric Blanc Kalray
{"title":"Demo: MPPA® manycore processor towards future ADAS system solutions","authors":"Pierre-Edouard Beaucamps, Frédéric Blanc Kalray","doi":"10.1109/DASIP.2016.7853834","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853834","url":null,"abstract":"This document describes a demonstration, proposed at DASIP Demo Night session. This demonstration is running on a low-power manycore processor from Kalray, named MPPA® and is highlighting capabilities of this new generation chip in processing multiple applications.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"3 1","pages":"243-244"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88805603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power consumption improvement with residue code for fault tolerance on SRAM FPGA 基于SRAM FPGA的容错剩余码的功耗改进
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2011-01-01 DOI: 10.1109/DASIP.2011.6136883
F. Amiel, T. Ea, Vashishtha Vinay
{"title":"Power consumption improvement with residue code for fault tolerance on SRAM FPGA","authors":"F. Amiel, T. Ea, Vashishtha Vinay","doi":"10.1109/DASIP.2011.6136883","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136883","url":null,"abstract":"","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"9 1","pages":"223-228"},"PeriodicalIF":0.0,"publicationDate":"2011-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73073112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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