2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)最新文献_第4页

Fuzzy logic modeling for objective image quality assessment 客观图像质量评价的模糊逻辑建模

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853803

Ghislain Takam Tchendjou, Rshdee Alhakim, E. Simeu

{"title":"Fuzzy logic modeling for objective image quality assessment","authors":"Ghislain Takam Tchendjou, Rshdee Alhakim, E. Simeu","doi":"10.1109/DASIP.2016.7853803","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853803","url":null,"abstract":"This paper presents a novel methodology of objective image quality assessment (IQA) based on Fuzzy Logic (FL) method. The main purpose is to automatically assess the quality of image in agreement with human visual perception. The used attributes (quality metrics) and evaluation criteria (human rating mean opinion score MOS) are extracted from image quality database TID2013. The fuzzy model design starts by selecting the most independent attributes, by applying Pearson's correlation approach and seeking the most correlated metrics with the corresponding MOS. Then, Adaptive Neuro-Fuzzy Inference System (ANFIS) is applied in order to construct an objective fuzzy model able to efficiently predict the image quality correlated with the subjective MOS. In this paper, different fuzzy models are produced by modifying certain ANFIS configurations. After that, we select the appropriate ANFIS model that provides high prediction accuracy and stability with taking into account its implementation complexity. The overall architecture of the selected FL model consists of four input metrics, two bell-shaped membership functions associated to each input metric, two fuzzy if-then rules, two linear combination equations and one output which gives the image adequate quality score. Finally the performance of the proposed fuzzy model is compared with other IQA models produced by different machine learning methods, the simulation results demonstrate that the fuzzy logic model has a high stable behavior with the best agreement with human visual perception.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"8 1","pages":"98-105"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88111893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Session 4: Advanced hardware architectures 第四部分:高级硬件架构

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853804

M. Biglari-Abhari

引用次数: 0

A system-level security approach for heterogeneous MPSoCs 异构mpsoc的系统级安全方法

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853800

Benjamin Tan, M. Biglari-Abhari, Z. Salcic

引用次数: 7

Session 1: HEVC in embedded systems 第一部分:嵌入式系统中的HEVC

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853789

E. Juárez

引用次数: 1

Efficient parallel architecture of an intra-only scalable multi-layer HEVC encoder 一种内部可扩展多层HEVC编码器的高效并行架构

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853790

Ronan Parois, W. Hamidouche, E. Mora, M. Raulet, O. Déforges

引用次数: 2

A dedicated lightweight binocular stereo system for real-time depth-map generation 用于实时深度图生成的专用轻量级双目立体系统

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853822

Trevor Gee, P. Delmas, Sylvain Joly, Valentin Baron, R. Ababou, J. Nezan

引用次数: 3

Hyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platform 基于大规模并行处理器阵列(MPPA)平台的线性支持向量机的高光谱图像分类

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853812

D. Madroñal, R. Lazcano, H. Fabelo, S. Ortega, G. Callicó, E. Juárez, C. Sanz

{"title":"Hyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platform","authors":"D. Madroñal, R. Lazcano, H. Fabelo, S. Ortega, G. Callicó, E. Juárez, C. Sanz","doi":"10.1109/DASIP.2016.7853812","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853812","url":null,"abstract":"In this paper, a study of the parallel exploitation of a Support Vector Machine (SVM) classifier with a linear kernel running on a Massively Parallel Processor Array platform is exposed. This system joins 256 cores working in parallel and grouped in 16 different clusters. The main objective of the research has been to develop an optimal implementation of the SVM classifier on a MPPA platform whilst the architectural bottlenecks of the hyperspectral image classifier are analyzed. Experimenting with medical images, the parallelization of the SVM classification has been conducted using three strategies: i) single- and multi-core processing, ii) single- and multi-cluster analysis and iii) single- and double-buffer execution. As a result, an average core processing speedup of 11.8 has been achieved when parallelizing the SVM classification process in a single cluster. On the contrary, since data communication accounts for 34.7% of the total execution time in the sequential case, the total speedup is upper-bounded to 2.9. Using a double-buffer methodology, a total speedup of 2.84 has been achieved on a single cluster. At last, the feasibility of a portable version of a linear SVM has been demonstrated.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"65 1","pages":"154-160"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80904092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Low power design methodology for signal processing systems using lightweight dataflow techniques 使用轻量级数据流技术的信号处理系统的低功耗设计方法

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853801

Lin Li, Tiziana Fanni, T. Viitanen, Renjie Xie, F. Palumbo, L. Raffo, H. Huttunen, J. Takala, S. Bhattacharyya

引用次数: 4

SystemC modelling of lossless compression IP cores for space applications 空间应用中无损压缩IP核的系统建模

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853798

Lucana Santos, A. Gomez, Pedro Hernandez-Fernandez, R. Sarmiento

{"title":"SystemC modelling of lossless compression IP cores for space applications","authors":"Lucana Santos, A. Gomez, Pedro Hernandez-Fernandez, R. Sarmiento","doi":"10.1109/DASIP.2016.7853798","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853798","url":null,"abstract":"In this paper, we perform the Electronic System Level (ESL) modelling and verification of two lossless compression standard algorithms for space applications using the SystemC language. In particular we present the architectures and a description in SystemC of the CCSDS-121 universal lossless compressor and the CCSDS-123 lossless compressor for hyperspectral and multispectral images. Both algorithms were specifically designed to operate on board satellites and they can be utilized as independent standalone compressors as well as jointly. In the latter case, the CCSDS-121 performs the entropy coding stage of the CCSDS-123 compressor. The computational capabilities of the hardware available on a satellite are limited, and hence, it is necessary to design hardware architectures that make it possible to execute the algorithms in an efficient way in terms of throughput, resource utilization and power consumption. On-board compression algorithms are usually implemented on ASICs or FPGAs that are tolerant to solar radiation. The main objective of this work is to describe models of the compressors in SystemC, that enable the generation of specifications for a subsequent implementation phase where the algorithms will be described in a hardware design language (VHDL) that can be efficiently mapped into space-qualified FPGAs. With the SystemC models, we perform an exploration of the design space, refining the architecture, and retrieving information about the limits in performance of the cores, storage requirements, data dependencies and prospective hardware requirements of the later FPGA implementation. The described models also comprise connections to shared communication buses using transaction-level modelling (TLM), allowing their inclusion in an embedded system model that may include a software co-processor as well as other processing cores. Additionally, the models are verified by creating SystemC testbenches that can be reused to verify the IP cores when described in VHDL.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"54 1","pages":"65-72"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75188808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Session 5: Image processing on multicore plateforms 第五部分:多核平台上的图像处理

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI: 10.1109/DASIP.2016.7853808

P. Langlois

引用次数: 0