2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)最新文献

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Fixed-Point Code Synthesis Based on Constraint Generation 基于约束生成的定点代码综合
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2022-01-01 DOI: 10.1007/978-3-031-12748-9_9
Sofiane Bessaï, Dorra Ben Khalifa, Hanane Benmaghnia, M. Martel
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引用次数: 1
Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems 嵌入式系统上简约CNN推理的动态剪枝
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2022-01-01 DOI: 10.1007/978-3-031-12748-9_4
Paola Busia, Ilias Theodorakopoulos, V. Pothos, N. Fragoulis, P. Meloni
{"title":"Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems","authors":"Paola Busia, Ilias Theodorakopoulos, V. Pothos, N. Fragoulis, P. Meloni","doi":"10.1007/978-3-031-12748-9_4","DOIUrl":"https://doi.org/10.1007/978-3-031-12748-9_4","url":null,"abstract":"","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"33 1","pages":"45-56"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78189425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low Latency Architecture Design for Decoding 5G NR Polar Codes 5G NR Polar码解码的低延迟架构设计
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2022-01-01 DOI: 10.1007/978-3-031-12748-9_2
Oualid Mouhoubi, C. A. Nour, A. Baghdadi
{"title":"Low Latency Architecture Design for Decoding 5G NR Polar Codes","authors":"Oualid Mouhoubi, C. A. Nour, A. Baghdadi","doi":"10.1007/978-3-031-12748-9_2","DOIUrl":"https://doi.org/10.1007/978-3-031-12748-9_2","url":null,"abstract":"","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"4 1","pages":"16-28"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74396171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
QoS Aware Design-Time/Run-Time Manager for FPGA-Based Embedded Systems 基于fpga的嵌入式系统QoS感知设计时/运行时管理器
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2022-01-01 DOI: 10.1007/978-3-031-12748-9_8
A. Duhamel, S. Pillement
{"title":"QoS Aware Design-Time/Run-Time Manager for FPGA-Based Embedded Systems","authors":"A. Duhamel, S. Pillement","doi":"10.1007/978-3-031-12748-9_8","DOIUrl":"https://doi.org/10.1007/978-3-031-12748-9_8","url":null,"abstract":"","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"19 1","pages":"96-107"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76718435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparative Study of Scheduling a Convolutional Neural Network on Multicore MCU 卷积神经网络在多核单片机上调度的比较研究
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2022-01-01 DOI: 10.1007/978-3-031-12748-9_6
Petr Dobiáš, Thomas Garbay, B. Granado, K. Hachicha, A. Pinna
{"title":"Comparative Study of Scheduling a Convolutional Neural Network on Multicore MCU","authors":"Petr Dobiáš, Thomas Garbay, B. Granado, K. Hachicha, A. Pinna","doi":"10.1007/978-3-031-12748-9_6","DOIUrl":"https://doi.org/10.1007/978-3-031-12748-9_6","url":null,"abstract":"","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"19 1","pages":"69-80"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89502298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influence of Dataflow Graph Moldable Parameters on Optimization Criteria 数据流图可塑参数对优化准则的影响
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2022-01-01 DOI: 10.1007/978-3-031-12748-9_7
Alexandre Honorat, Thomas Bourgoin, Hugo Miomandre, K. Desnos, D. Ménard, J. Nezan
{"title":"Influence of Dataflow Graph Moldable Parameters on Optimization Criteria","authors":"Alexandre Honorat, Thomas Bourgoin, Hugo Miomandre, K. Desnos, D. Ménard, J. Nezan","doi":"10.1007/978-3-031-12748-9_7","DOIUrl":"https://doi.org/10.1007/978-3-031-12748-9_7","url":null,"abstract":"","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"45 1","pages":"83-95"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85684445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Exploring Fully Convolutional Networks for the Segmentation of Hyperspectral Imaging Applied to Advanced Driver Assistance Systems 探索用于高级驾驶辅助系统的高光谱图像分割的全卷积网络
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2022-01-01 DOI: 10.1007/978-3-031-12748-9_11
Jon Gutiérrez-Zaballa, Koldo Basterretxea, J. Echanobe, M. V. Martínez, I. D. Campo
{"title":"Exploring Fully Convolutional Networks for the Segmentation of Hyperspectral Imaging Applied to Advanced Driver Assistance Systems","authors":"Jon Gutiérrez-Zaballa, Koldo Basterretxea, J. Echanobe, M. V. Martínez, I. D. Campo","doi":"10.1007/978-3-031-12748-9_11","DOIUrl":"https://doi.org/10.1007/978-3-031-12748-9_11","url":null,"abstract":"","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"1 1","pages":"136-148"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90739700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
DL-CapsNet: A Deep and Light Capsule Network DL-CapsNet:一个深而轻的胶囊网络
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2022-01-01 DOI: 10.1007/978-3-031-12748-9_5
Pouya Shiri, A. Baniasadi
{"title":"DL-CapsNet: A Deep and Light Capsule Network","authors":"Pouya Shiri, A. Baniasadi","doi":"10.1007/978-3-031-12748-9_5","DOIUrl":"https://doi.org/10.1007/978-3-031-12748-9_5","url":null,"abstract":"","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"1 1","pages":"57-68"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77237188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices 用于多核设备硬输入LDPC解码的高性能Gallager-E解码器
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2022-01-01 DOI: 10.1007/978-3-031-12748-9_1
B. Gal, Vincent Pignoly, C. Jégo
{"title":"High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices","authors":"B. Gal, Vincent Pignoly, C. Jégo","doi":"10.1007/978-3-031-12748-9_1","DOIUrl":"https://doi.org/10.1007/978-3-031-12748-9_1","url":null,"abstract":"","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"1 1","pages":"3-15"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82695154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DASIP '21: Workshop on Design and Architectures for Signal and Image Processing (14th edition) - in conjunction with HiPEAC 2021, Budapest, Hungary, January 18-20, 2021 DASIP '21:信号和图像处理的设计和架构研讨会(第14版)-与HiPEAC 2021一起,匈牙利布达佩斯,2021年1月18日至20日
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引用次数: 0
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