1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)最新文献_第8页

Cycle time and slack optimization for VLSI-chips vlsi芯片的周期时间和松弛优化

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810654

Christoph Albrecht, B. Korte, Jürgen Schietke, J. Vygen

{"title":"Cycle time and slack optimization for VLSI-chips","authors":"Christoph Albrecht, B. Korte, Jürgen Schietke, J. Vygen","doi":"10.1109/ICCAD.1999.810654","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810654","url":null,"abstract":"We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes all previously considered models. Then we show how to optimize the cycle time and optimally balance slacks on data paths and on clocktree paths. The problem of finding a clock schedule with the optimum cycle time was solved before, either by linear programming or by binary search, using a test for negative circuits in a digraph as a subroutine. We show for the first time that a direct combinatorial algorithm solves this problem optimally. Incidentally, this yields a new efficient method for timing analysis with transparent latches. Moreover, we extend this algorithm to the slack balancing problem: To make the chip less sensitive to routing detours, process variations and manufacturing skew it is desirable to have as few critical paths as possible. We show how to find the clock schedule with minimum number of critical paths (optimum slack distribution) in a well-defined sense. Rather than fixed dock arrival times we show how to obtain as large as possible intervals for the clock arrival times. This can be considered as slack on clocktree paths. Indeed, we can find the global optimum of simultaneous optimization of slacks on all data paths and clocktree paths. All the above is done by very efficient network optimization algorithms, based on parametric shortest paths. Our computational results with recent IBM processor chips show that the number of critical paths decreases dramatically, in addition to a considerable improvement of the cycle time. The running times are reasonable even for the largest designs.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78575780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 59

The Chebyshev expansion based passive model for distributed interconnect networks 基于Chebyshev展开的分布式互联网络无源模型

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810677

Janet Roveda, E. Kuh, Qingjian Yu

引用次数: 7

JMTP: an architecture for exploiting concurrency in embedded Java applications with real-time considerations jms:一种架构，用于利用嵌入式Java应用程序中的并发性，并考虑到实时性

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810710

Rachid Helaihel, K. Olukotun

{"title":"JMTP: an architecture for exploiting concurrency in embedded Java applications with real-time considerations","authors":"Rachid Helaihel, K. Olukotun","doi":"10.1109/ICCAD.1999.810710","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810710","url":null,"abstract":"Using Java in embedded systems is plagued by problems of limited runtime performance and unpredictable runtime behavior. The Java Multi-Threaded Processor (JMTP) provides solutions to these problems. The JMTP architecture is a single chip containing an off-the-shelf general purpose processor core coupled with an array of Java Thread Processors (JTPs). Performance can be improved using this architecture by exploiting coarse-grained parallelism in the application. These performance improvements are achieved with relatively small hardware costs. Runtime predictability is improved by implementing a subset of the Java Virtual Machine (JVM) specification in the JTP and trimming away complexity without excessively restricting the Java code a JTP can handle. Moreover the JMTP architecture incorporates hardware to adaptively manage shared JMTP resources in order to satisfy JTP thread timing constraints or provide an early warning for a timing violation. This is an important feature for applications with quality-of-service demands. In addition to the hardware architecture, we describe a software framework that analyzes a Java application for expressed and implicit coarse-grained concurrent threads to execute on JTPs. This framework identifies the optimal mapping of an application to a JMTP with an arbitrary number of JTPs. We have tested this framework on a variety of applications including IDEA encryption with different JTP configurations and confirmed that the algorithm was able to obtain desired results in each case.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73699571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Electromagnetic parasitic extraction via a multipole method with hierarchical refinement 基于多极子分层改进的电磁寄生提取方法

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810690

M. Beattie, L. Pileggi

{"title":"Electromagnetic parasitic extraction via a multipole method with hierarchical refinement","authors":"M. Beattie, L. Pileggi","doi":"10.1109/ICCAD.1999.810690","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810690","url":null,"abstract":"The increasing interconnect density and operating frequencies of system-on-a-chip (SOC) designs necessitates extraction of parasitic electromagnetic couplings beyond the localized confines of functional design blocks. In addition, SOC design styles and gridless variable-width routing make it increasingly difficult to use precharacterized library shapes for parasitic extraction. A comprehensive capacitance and inductance extraction solution requires a hierarchical data representation and fast runtime algorithms. We illustrate through examples that both the multipole method and hierarchical refinement, which are the two most successful approaches for parasitic extraction to date, work efficiently only under certain, limiting conditions. To improve this situation we present an approach which combines the best of both methods into a concurrent multipole refinement representation of the electromagnetic interaction which is efficient for arbitrary interconnect configurations. We use a generalized formulation of electromagnetic interactions to exploit the similarities in capacitance and inductance extraction for greater efficiency.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73806061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

A scalable substrate noise coupling model for mixed-signal ICs 混合信号集成电路的可扩展衬底噪声耦合模型

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810636

A. Samavedam, K. Mayaram, T. Fiez

引用次数: 10

Copy detection for intellectual property protection of VLSI designs VLSI设计知识产权保护中的复制检测

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810718

A. Kahng, D. Kirovski, S. Mantik, M. Potkonjak, J. Wong

引用次数: 51

LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay LEOPARD:一个基于逻辑努力的区域和延迟扇出优化器

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810704

P. Rezvani, A. Ajami, Massoud Pedram, H. Savoj

引用次数: 22

OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic OPTIMISTA:异步FSMs的状态最小化，以获得最佳输出逻辑

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810610

Robert M. Fuhrer, S. Nowick

{"title":"OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic","authors":"Robert M. Fuhrer, S. Nowick","doi":"10.1109/ICCAD.1999.810610","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810610","url":null,"abstract":"The optimal state minimization problem is to select a reduced state machine having the best logic implementation over all possible state reductions and encodings. The OPTIMIST (OPTImal MInimization of STates) algorithm (R.M. Fuhrer et al., 1997) was the first general solution to this problem for synchronous finite state machines (FSMs). In this paper, we present the first solution for asynchronous FSMs. This paper makes two contributions. First, we introduce OPTIMISTA (OPTIMIST-Asynchronous), a new algorithm which guarantees optimum 2-level output logic for asynchronous FSMs. In asynchronous machines, output logic is often critical: it usually determines the machine latency. The algorithm is formulated as a binate constraint satisfaction problem, which is solved using a binate solver. The second contribution is a novel alternative result: the unreduced machine itself can be used directly to obtain minimum-cardinality output logic. Thus, this paper presents two approaches: using OPTIMISTA, which simultaneously performs state and logic minimization; or using no state reduction (if output logic cardinality is of sole interest). Extensions for literal optimization, targetted to multi-level logic, are also proposed.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86899665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

On the global fanout optimization problem 关于全局扇出优化问题

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810703

R. Murgai

引用次数: 33

Dynamic power management using adaptive learning tree 动态电源管理使用自适应学习树

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810661

Eui-Young Chung, L. Benini, G. Micheli

引用次数: 175