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2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems最新文献

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A symbolic RTL synthesis for LUT-based FPGAs 基于lut的fpga的符号RTL合成
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012107
S. Deniziak, M. Wisniewski
{"title":"A symbolic RTL synthesis for LUT-based FPGAs","authors":"S. Deniziak, M. Wisniewski","doi":"10.1109/DDECS.2009.5012107","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012107","url":null,"abstract":"In this paper a methodology of symbolic RTL synthesis, for circuits implemented in FPGA devices, is presented. First, symbolic functions are separated from binary and arithmetic ones. Next, the multi-valued logic network is optimized using our methods of symbolic functional decomposition, designed for functions with multi-valued inputs and multi-valued outputs. Finally, the whole circuit is implemented in FPGA device using commercially available tools. The goal of the presented methodology is to minimize the total FPGA area. Presented example showed that our methodology gives better results than existing RTL synthesis tools.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"16 1","pages":"102-107"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81741697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A fast untestability proof for SAT-based ATPG 基于sat的ATPG的快速不可测性证明
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012096
Daniel Tille, R. Drechsler
{"title":"A fast untestability proof for SAT-based ATPG","authors":"Daniel Tille, R. Drechsler","doi":"10.1109/DDECS.2009.5012096","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012096","url":null,"abstract":"Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. SAT solvers work on instances given in Conjunctive Normal Form (CNF). The required transformation of the ATPG problem into CNF is one main part of SAT-based ATPG and needs a significant portion of the overall run time. Solving the SAT instance is the other main part. Here, the time needed is often negligible - especially for easy-to-classify untestable faults. This paper presents a preprocessing technique that speeds up the classification of untestable faults by accelerating the SAT instance generation. This increases the robustness of the entire ATPG process. The efficiency of the proposed method is shown by experiments on large industrial designs.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"212 1","pages":"38-43"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73617661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Fast congestion-aware timing-driven placement for island FPGA 岛式FPGA的快速拥塞感知时序驱动布局
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012092
Jinpeng Zhao, Qiang Zhou, Yici Cai
{"title":"Fast congestion-aware timing-driven placement for island FPGA","authors":"Jinpeng Zhao, Qiang Zhou, Yici Cai","doi":"10.1109/DDECS.2009.5012092","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012092","url":null,"abstract":"A new fast timing-driven placement is presented in this paper, which is partitioning-based method, explicitly considering the congestion for island style FPGAs. The most distinct feature of this approach is that it not only reduces the circuit critical path delay efficiently, but also takes congestion into account. The harmony between partitioning objective and timing improvement goal is kept; moreover, the congestion constraint is added to cost function to improve routability in the meantime. As a result, it avoids the excessive usage of local routing resources while remaining circuit performance much better. The experimental results show our method, FCTP, is very fast. It is able to produce solutions with equal or better routability and up to average 8.19% improvement on performance but only less 1/3 average runtime compared to TVPR [1]. It also achieves much better results than PPFF [7] in terms of timing and congestion with negligible runtime penalty.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"10 19 1","pages":"24-27"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88826188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance 全数字基带50 Mbps数据恢复使用5倍过采样与0.9数据单位间隔时钟抖动容限
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012129
Sanad Bushnaq, T. Nakura, M. Ikeda, K. Asada
{"title":"All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance","authors":"Sanad Bushnaq, T. Nakura, M. Ikeda, K. Asada","doi":"10.1109/DDECS.2009.5012129","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012129","url":null,"abstract":"In this paper, an all digital baseband data recovery algorithm using oversampling technique is presented. Our algorithm uses 5× clock to sample incoming data once around the middle. Sampling occurs exactly on the third clock after a data edge. If no data edge sensed, sampling occurs after five clocks from the previous sample. The system is designed to receive 50 Mbps data bit rate and uses a 250 MHz local clock to do the oversampling process. After injecting the clock with jitter at various magnitudes and frequencies, the design showed around 0.9 data Unit Interval (UIdata) jitter tolerance at frequencies higher than 25 MHz, in addition to a low Bit Error Rate (BER ≪ 10−11). The setup is implemented on an Altera Stratix II GX Field Programmable Gate Array (FPGA) while Agilent 81250 parallel Bit Error Ratio Tester (parBERT) is used to measure BER using Pseudo Random Bit Sequences (PRBS). Using 0.18 µm CMOS process, the design consumes as low power as 5 µW, which makes it effective for low power applications such as wireless image sensor nodes.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"32 1","pages":"206-209"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87818825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs 基于fpga的增强型低成本测试平台，为soc提供有效的测试数据压缩
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012141
Lyl M. Ciganda Brasca, F. Abate, P. Bernardi, M. Bruno, M. Reorda
{"title":"An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs","authors":"Lyl M. Ciganda Brasca, F. Abate, P. Bernardi, M. Bruno, M. Reorda","doi":"10.1109/DDECS.2009.5012141","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012141","url":null,"abstract":"Reducing the cost of test (in particular by reducing its duration and the cost of the required ATE) is a common goal which has largely been pursued in the past, mainly by introducing suitable on chip Design for Testability (DfT) circuitry. Today, the increasing popularity of sophisticated DfT architectures and the parallel emergence of new ATE families allow the identification of innovative solutions effectively facing that goal. In this paper we face the increasingly common situation of SoCs adopting the IEEE 1149.1 and 1500 standards for the test of the internal cores, and explore the idea of storing the test program on the tester in a compressed form, and decompressing it on-the-fly during test application.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":" 1","pages":"258-263"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91414122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Global parametric faults identification with the use of Differential Evolution 基于差分进化的全局参数故障识别
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012133
P. Jantos, D. Grzechca, J. Rutkowski
{"title":"Global parametric faults identification with the use of Differential Evolution","authors":"P. Jantos, D. Grzechca, J. Rutkowski","doi":"10.1109/DDECS.2009.5012133","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012133","url":null,"abstract":"This paper presents a novel method to a multiple parametric faults diagnosis (global parametric faults - GPF) in analogue integrated circuits (AIC). The method is based on features of AIC time domain response to voltage step excitation, i.e. AIC response and its first order derivative maxima and minima locations. A circuit states classification is acquired with the use of linear evolutionary classifier which parameters are determined with the use of Differential Evolution. Selected AIC response features distributions are approximated with geometric figures based on polynomial functions. The proposed diagnosis method has been applied for a GPF diagnosis in an exemplary integrated circuit - operational amplifier µ4741.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"17 1","pages":"222-225"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84793878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Simulation and planning method for on-chip power distribution — An industry perspective 片上电源分配的仿真和规划方法-工业观点
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012122
Qing K. Zhu, Vincent Bars
{"title":"Simulation and planning method for on-chip power distribution — An industry perspective","authors":"Qing K. Zhu, Vincent Bars","doi":"10.1109/DDECS.2009.5012122","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012122","url":null,"abstract":"Power grid's planning in the early design stage is hard, but critical for the layout area and circuit performance. Full-chip level's accurate mathematical modeling of switching currents in the power grid is an almost impossible mission, although many previous research works have been existed [6–9]. We introduce two industry methods for the power distribution planning in the early design stage, especially in the region of standard cells as well as the full chip level. Modeling details of “simplified” current sources, for the full-chip power grid simulation in the early planning, are explained for one SOC example in the paper.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"1 1","pages":"174-177"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83849669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOS 用于65nm CMOS的DVB-H接收机的1GHz-GBW运算放大器
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012124
H. Uhrmann, Franz Schlögl, K. Schweiger, H. Zimmermann
{"title":"A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOS","authors":"H. Uhrmann, Franz Schlögl, K. Schweiger, H. Zimmermann","doi":"10.1109/DDECS.2009.5012124","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012124","url":null,"abstract":"The offer of information grows rapidly in mobile markets. The DVB-H standard as a part of DVB-T is an important carrier of information to a broad spectrum of consumers. New, cheap and robust receivers have to be developed, especially for handheld devices. We propose a high-speed operational amplifier for a low-pass filter in a direct conversion receiver. In order to integrate the receiver on a System on Chip, it is designed in 65nm low-power CMOS. The operational amplifier is a four-stage feed-forward nested Miller compensated fully differential operational amplifier with an AB output stage. A gain-bandwidth product of 1GHz and a gain of 58dB is reached. A load capacitance of 5pF can be driven at a phase margin of 62deg.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"1 1","pages":"182-185"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89951706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio MDCT / IMDCT低功耗实现在90纳米CMOS技术的MP3音频
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012116
P. Malík, Michal Ufnal, A. W. Luczyk, M. Baláz, W. Pleskacz
{"title":"MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio","authors":"P. Malík, Michal Ufnal, A. W. Luczyk, M. Baláz, W. Pleskacz","doi":"10.1109/DDECS.2009.5012116","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012116","url":null,"abstract":"MDCT is the basic processing component for high quality audio compression. It is also the most computationally intensive operation in the vast majority of audio compression standards. Mostly used audio standard for audio compression is still MP3. This paper presents new implementations of five MDCT / IMDCT architectures with different parallelization levels for MP3. Implementation utilize UMC 90 nm CMOS technology. Design was optimized for low power applications. Low power libraries and clock gating technique were used for power reduction. All IP cores are capable of computing forward and backward MDCT and this feature makes them universal in multimedia SoCs for accelerating the MP3 audio compression/decompression.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"196 1","pages":"144-147"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77654447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
MTPP - Modular Traffic Processing Platform MTPP——模块化流量处理平台
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012121
Jiri Halak, S. Ubik
{"title":"MTPP - Modular Traffic Processing Platform","authors":"Jiri Halak, S. Ubik","doi":"10.1109/DDECS.2009.5012121","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012121","url":null,"abstract":"High-speed (10 Gb/s and above) network monitoring and traffic processing requires hardware acceleration. Different applications require different functions to be placed in hardware. Current packet capture cards include fixed firmware, which is difficult to extend. In this paper we propose an architecture for Modular Traffic Processing Platform (MTPP), which enables end users to easily modify hardware processing without any FPGA development. On the other hand, developers can create new processing modules with much reduced effort thanks to simple module interfaces and isolation of module time constraints.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"9 1","pages":"170-173"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83668270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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