IBM Journal of Research and Development最新文献_第5页

Integration of z15 processor-based DEFLATE acceleration into IBM z/OS 将基于z15处理器的DEFLATE加速集成到IBM z/OS中

IF 1.3 4区计算机科学

IBM Journal of Research and Development Pub Date : 2020-07-10 DOI: 10.1147/JRD.2020.3008101

A. T. Sofia;M. Klein;B. D. Stilwell;S. Weishaupt;Q. Y. Chen;R. W. St John

{"title":"Integration of z15 processor-based DEFLATE acceleration into IBM z/OS","authors":"A. T. Sofia;M. Klein;B. D. Stilwell;S. Weishaupt;Q. Y. Chen;R. W. St John","doi":"10.1147/JRD.2020.3008101","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008101","url":null,"abstract":"IBM z15 replaces the former I/O attached accelerator for DEFLATE, zEnterprise Data Compression (zEDC) Express, with an on-chip accelerator that can be synchronously accessed via an instruction. The integration of this new accelerator in the z/OS software stack has been designed to maintain a consistent user experience for software packages that used the previous technology, while still allowing the enhanced aspects of the new technology to deliver the additional value. Two different access paths for DEFLATE have been created in z/OS to accomplish both goals. For user space programs that utilize the zlib API, z/OS directly executes the instruction synchronously, which avoids overhead and reduces latency. Authorized users continue to utilize existing infrastructure and have the Service Assist Processors (SAP) perform compression in an asynchronous fashion on their behalf. The SAP receives information about the requested task via a thin and efficient communication path to z/OS, invokes the instruction in a well-defined fashion, and returns the result to z/OS. \u0000<p>This article describes the integration of DEFLATE acceleration in z15 into the z/OS software stack in both synchronous and asynchronous mode and presents the resulting performance for selected workloads.</p>","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008101","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IBM Z in a secured hybrid cloud IBM Z在一个安全的混合云中

IF 1.3 4区计算机科学

IBM Journal of Research and Development Pub Date : 2020-07-10 DOI: 10.1147/JRD.2020.3008111

A. Bieswanger;A. Maier;C. Mayer;H. Shah;J. Candee

引用次数: 0

System Recovery Boost on IBM z15 IBM z15上的系统恢复增强

IF 1.3 4区计算机科学

IBM Journal of Research and Development Pub Date : 2020-07-10 DOI: 10.1147/JRD.2020.3008102

D. H. Surman;S. Lederer;D. B. Petersen;M. Gubitz;P. J. Relson

{"title":"System Recovery Boost on IBM z15","authors":"D. H. Surman;S. Lederer;D. B. Petersen;M. Gubitz;P. J. Relson","doi":"10.1147/JRD.2020.3008102","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008102","url":null,"abstract":"System Recovery Boost on the IBM z15 server expedites planned operating system shutdown, either planned or unplanned operating system initial program load (IPL), middleware and workload restart and recovery, and the client workload execution that follows, to accelerate service restoration around downtime. It does this by providing limited-duration “boost periods” that deliver significant usable additional processor capacity and parallelism. On subcapacity machine models, it provides a boost in processor speed by running the general-purpose processors at full-capacity speed, for the boosting LPARs only, and only during the boost periods. It makes all available processing capacity defined to the boosting images available to process any kind of work, “blurring” general-purpose processor and specialty processor capacity together during the boost period. System Recovery Boost also expedites and parallelizes processor reconfiguration actions that may be part of the client's overall restart and recovery process, as orchestrated by Geographically Dispersed Parallel Sysplex (GDPS) automation. Optionally, System Recovery Boost provides the ability to add additional processor capacity from the client's unused “dark cores” via activation of a new type of temporary capacity record. All of this can be accomplished without increasing the client's IBM software billing costs or the processor consumption associated with the client's workload during these boost periods.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008102","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49979349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IBM z15: Physical design improvements to significantly increase content in the same technology IBM z15:物理设计改进，以显著增加相同技术中的内容

IF 1.3 4区计算机科学

IBM Journal of Research and Development Pub Date : 2020-07-10 DOI: 10.1147/JRD.2020.3008099

C. J. Berry;D. Wolpert;B. Bell;A. Jatkowski;J. Surprise;G. Strevig;J. Isakson;O. Geva;B. Deskin;M. Cichanowski;G. Biran;D. Hamid;C. Cavitt;G. Fredeman;D. Chidambarrao;B. Bruen;M. Wood;S. Carey;D. Turner;L. Sigal

{"title":"IBM z15: Physical design improvements to significantly increase content in the same technology","authors":"C. J. Berry;D. Wolpert;B. Bell;A. Jatkowski;J. Surprise;G. Strevig;J. Isakson;O. Geva;B. Deskin;M. Cichanowski;G. Biran;D. Hamid;C. Cavitt;G. Fredeman;D. Chidambarrao;B. Bruen;M. Wood;S. Carey;D. Turner;L. Sigal","doi":"10.1147/JRD.2020.3008099","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008099","url":null,"abstract":"The IBM Z processor continues to improve over previous System Z processors, but for the first time it does so without a technology improvement as the baseline enabler. The IBM z15 was designed in the same 14-nm High-Performance GLOBALFOUNDRIES technology as the IBM z14 and yet still added 20% more cores, doubled the L3 cache, and increased the L2 cache by a third while also adding a third peripheral component interconnect express (PCIe) port to the chip and an elliptic curve cryptography engine into each core. This article discusses the design, tool, and methodology enhancements required to increase the design content so significantly while maintaining the chip size and power limits from the previous z14 design. This article also discusses other design and methodology improvements that were made possible via the deeper understanding of the technology and how to more fully leverage it in a second generation.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008099","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design and verification of DEFLATE acceleration as an architected instruction in z15 z15体系结构指令DEFLATE加速度的设计与验证

IF 1.3 4区计算机科学

IBM Journal of Research and Development Pub Date : 2020-07-10 DOI: 10.1147/JRD.2020.3008106

M. Klein;A. Misra;B. Abali;P. Sethia;S. Weishaupt;B. Giamei;M. Farrell;T. J. Slegel

{"title":"Design and verification of DEFLATE acceleration as an architected instruction in z15","authors":"M. Klein;A. Misra;B. Abali;P. Sethia;S. Weishaupt;B. Giamei;M. Farrell;T. J. Slegel","doi":"10.1147/JRD.2020.3008106","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008106","url":null,"abstract":"The IBM z15 processor chip contains a new hardware component to perform DEFLATE compliant compression and decompression. The Integrated Accelerator for zEnterprise Data Compression is based on a high-frequency DEFLATE pipeline and includes a hardware generator for dynamic Huffman tables. Accessible as an architected instruction, this engine has been designed for straight forward exploitation by software and is easily available to any application in the problem state. A brand-new hardware/firmware integration model has been developed to provide this complex functionality without imposing restrictions on data patterns or data sizes and without impacting system responsiveness. This article describes the concept, implementation, and verification of DEFLATE compliant compression acceleration in z15 across both hardware and firmware. It illustrates various challenges that result from incorporating complex data-dependent and data-intense functionality like DEFLATE as an architected instruction and discusses how solutions in hardware/firmware codesign have been applied to overcome these challenges.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008106","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The IBM 4769 Cryptographic Coprocessor IBM 4769加密协处理器

IF 1.3 4区计算机科学

IBM Journal of Research and Development Pub Date : 2020-07-10 DOI: 10.1147/JRD.2020.3008145

J. A. Busby;E. N. Cohen;E. A. Dames;J. Doherty;S. Dragone;D. Evans;M. J. Fisher;N. Hadzic;C. Hagleitner;A. J. Higby;M. D. Hocker;L. S. Jagich;M. J. Jordan;R. Kisley;K. D. Lamb;M. D. Marik;J. Mayfield;T. E. Morris;T. D. Needham;W. Santiago-Fernandez;V. Urban;T. Visegrady;K. Werner

{"title":"The IBM 4769 Cryptographic Coprocessor","authors":"J. A. Busby;E. N. Cohen;E. A. Dames;J. Doherty;S. Dragone;D. Evans;M. J. Fisher;N. Hadzic;C. Hagleitner;A. J. Higby;M. D. Hocker;L. S. Jagich;M. J. Jordan;R. Kisley;K. D. Lamb;M. D. Marik;J. Mayfield;T. E. Morris;T. D. Needham;W. Santiago-Fernandez;V. Urban;T. Visegrady;K. Werner","doi":"10.1147/JRD.2020.3008145","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008145","url":null,"abstract":"System security is currently a main focus area for all IT infrastructure providers. New system features like pervasive encryption, the transition to cloud-based offerings, and the demand for quantum-safe platforms demand increased cryptographic performance as well as more cryptographic agility. The new IBM 4769 Cryptographic Coprocessor addresses these trends. It brings performance improvements that match the requirements of the new IBM z15. A combination of newly available features allows IBM z15 to scale to greater than 5,000 Virtual Hardware secure modules per system and makes it suitable to support virtualized client environments such as cloud-scale datacenters. To meet the dense packaging and energy requirements of those data centers, the form factor and power consumption of the card were reduced significantly. The card also offers an expanded set of algorithms to support state-of-the-art as well as future workloads. For the first time, the user interface provides access to a selected set of quantum-safe algorithms. Infrastructure extensions add hardware-embedded, attestation-friendly trusted boot services, which improve system resiliency by providing hardware enabled measurements of the secure and trusted boot process. These extensions simultaneously simplify the security certifications built on them. This article provides an overview of the IBM 4769 cryptographic coprocessor, highlighting security characteristics, internal hardware, form factor, and enhanced firmware.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008145","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Partition placement by PR/SM 通过PR/SM放置分区

IF 1.3 4区计算机科学

IBM Journal of Research and Development Pub Date : 2020-07-10 DOI: 10.1147/JRD.2020.3008104

M. Somasundaram;J. P. Kubala;S. E. Lederer;J. Chan

{"title":"Partition placement by PR/SM","authors":"M. Somasundaram;J. P. Kubala;S. E. Lederer;J. Chan","doi":"10.1147/JRD.2020.3008104","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008104","url":null,"abstract":"Every new machine generation of IBM Z brings with it an increase in number of physical processors and memory capacity. Some generations can also bring change in the physical configuration of the server. The z15 for example, can have from one to five drawers instead of a maximum of four on the z14. As another example, z15 has fixed two chips per node versus the two or three chips per node on z14. The logical partitions on the other hand can come in various configurations, including “Dedicated” logical partition, shared “Hiperdispatch = YES” logical partition, and shared “Hiperdispatch = NO” partition. Each of the partition types can request as many logical processors and memory as the machine generation will allow, which is usually less than the physical resources available on the machine. The optimal placement of logical partitions on the physical server, given its configuration, is an NP-hard problem. Memory access latency and cache usage play vital roles in the performance of logical partitions, and it is imperative that placement is optimal. Moreover, on z15, the integrated facility for linux processors and internal coupling facility processors can be moved from one chip to another, during reoptimization of partition placement, in addition to general-purpose and IBM Z integrated information processors that are already allowed to be moved, compounding the placement problem. This article describes the changes made to the Processor Resource/Systems Manager (PR/SM) heuristic placement algorithm for z15 and how it surmounts the problems inherent for optimal placement of logical partitions.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008104","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IBM z15: Improved data center density and energy efficiency, new system packaging, and modeling IBM z15:改进的数据中心密度和能源效率，新的系统封装和建模

IF 1.3 4区计算机科学

IBM Journal of Research and Development Pub Date : 2020-07-10 DOI: 10.1147/JRD.2020.3008100

W. P. Kostenko;J. G. Torok;D. W. Demetriou

{"title":"IBM z15: Improved data center density and energy efficiency, new system packaging, and modeling","authors":"W. P. Kostenko;J. G. Torok;D. W. Demetriou","doi":"10.1147/JRD.2020.3008100","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008100","url":null,"abstract":"The IBM z15 is designed to meet the requirements of a range of data centers, while reducing costs through increased density, configuration flexibility, and cooling efficiency. The z15 is a continuation and broadening of the physical transformation of the mainframe that began with the IBM z14 ZR1/LR1, which introduced the new “true 19-in” frame. A maximum configuration z15 delivers greater than 30% additional compute capacity per watt than z14, and maintains approximately the same maximum system footprint, while enabling significant floor space reduction for most configurations. The z15 introduces the choice of integrated 2N power using either intelligent power distribution units or bulk power, also supporting most data centers including hot/cold-aisle containment, raised-floor and nonraised-floor, and top and bottom-exit I/O and power. The z15 supports the ASHRAE A3 (fourth edition) environment, providing efficiency advantages by reducing humidification requirements. The z15 maintains the value of a system that is preconfigured/pretested before shipping. Innovations in packaging, I/O cabling, controls, and testing are put in the context of the latest data center trends. The capabilities of new tools to estimate power, weight, airflow, heat extracted to water for water-cooled systems as well as 3-D and computational fluid dynamics models to aid in the planning for the system are described.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008100","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Proactive power management in IBM z15 IBM z15中的主动电源管理

IF 1.3 4区计算机科学

IBM Journal of Research and Development Pub Date : 2020-07-10 DOI: 10.1147/JRD.2020.3008143

T. Webel;P. M. Lobo;T. Strach;P. B. Parashurama;S. Purushotham;R. Bertran;A. Buyuktosunoglu

{"title":"Proactive power management in IBM z15","authors":"T. Webel;P. M. Lobo;T. Strach;P. B. Parashurama;S. Purushotham;R. Bertran;A. Buyuktosunoglu","doi":"10.1147/JRD.2020.3008143","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008143","url":null,"abstract":"The IBM z15 processor power management enhances several on-chip power management techniques over z14 processor with a specific focus on reducing response time for voltage droop management. The IBM z15 processor puts a specific emphasis on proactive voltage droop management strategy to reduce conservative static guard band that is added to the supply voltage in order to protect against worst-case voltage droops. The z15 processor relies on selected events from the earlier stages of a deep pipeline processor as indicators to predict sharp changes in the power consumption over a short period of time. The early information of the selected events allows to throttle the execution flow through the processor pipeline and prevents the sharp power change before it takes place and thus reduces the voltage droop. In z15, as one of the proactive schemes, we combine both the digital power-proxies, which are direct indicators of the processor activity and the Critical Path Monitors (CPMs) to give an earlier and proactive indication of voltage droop events. This proactive indication provides enough time for the throttle actuation circuits to prevent the voltage droop. CPMs act as real-time timing margin indicators, and power-proxies act to serve as the activity monitors.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008143","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Design of the IBM z15 microprocessor IBM z15微处理器的设计

IF 1.3 4区计算机科学

IBM Journal of Research and Development Pub Date : 2020-07-10 DOI: 10.1147/JRD.2020.3008119

A. Saporito;M. Recktenwald;C. Jacobi;G. Koch;D. P. D. Berger;R. J. Sonnelitter;C. R. Walters;J.-S. Lee;C. Lichtenau;U. Mayer;E. Herkel;S. Payer;S. M. Mueller;V. K. Papazova;E. M. Ambroladze;T. C. Bronson

引用次数: 3