2011 IEEE Radio Frequency Integrated Circuits Symposium最新文献_第8页

A dual-band digital TV tuner for CMMB application SoC 双频数字电视调谐器的CMMB应用SoC

2011 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2011-06-05 DOI: 10.1109/RFIC.2011.5940675

Huijung Kim, Sanghoon Kang, Jeong-Hyun Choi, Taewan Kim, Bo-Wei Lee, Jong-Dae Bae, Wooseung Choo, Hojin Park, Byeong-ha Park

引用次数: 4

A 12-bit resolution, 200-MSample/second phase modulator for a 2.5GHz carrier with discrete carrier pre-rotation in 65nm CMOS 一个12位分辨率，200-MSample/second phase调制器，用于2.5GHz载波，65nm CMOS离散载波预旋转

2011 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2011-06-05 DOI: 10.1109/RFIC.2011.5940597

T. Barton, SungWon Chung, P. Godoy, J. Dawson

引用次数: 10

CMOS digital tunable capacitance with tuning ratio up to 13 and 10dBm linearity for RF and millimeterwave design CMOS数字可调谐电容，调谐比高达13和10dBm线性度，用于射频和毫米波设计

2011 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2011-06-05 DOI: 10.1109/RFIC.2011.5940648

R. Debroucke, A. Pottrain, D. Titz, F. Gianesello, D. Gloria, C. Luxey, C. Gaquière

{"title":"CMOS digital tunable capacitance with tuning ratio up to 13 and 10dBm linearity for RF and millimeterwave design","authors":"R. Debroucke, A. Pottrain, D. Titz, F. Gianesello, D. Gloria, C. Luxey, C. Gaquière","doi":"10.1109/RFIC.2011.5940648","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940648","url":null,"abstract":"Nowadays capabilities offered by advanced silicon technologies enable both mmw design and agile circuits development, then the development of high performance tunable capacitance is now mandatory. One of the challenge to develop this component is to be able to design capacitance with a tuning range higher than 4 from RF up to millimeter wave range. Variable capacitance like MOS varactor does not meet circuit specifications due to their low tuning range and very high non linearity. Digital capacitances are a good candidate to address that need and this paper review the design, optimization and characterization of digital tunable capacitance (DTC). Specific DTC with series or traveling wave architecture are also address, allowing to synthesize high performance capacitance up to 110GHz regarding 10dBm linearity and a tuning ratio equal to 13. Those developments have been carried out using STMicroelectronics BiCMOS 0.13um millimeter wave technology. Finally, the design of a 60GHz Reflection Type Phase Shifter (RTPS) using 4 bits DTC is presented showing insertion loss less than 6dB and a phase shift of 62°.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130696550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

An active filter achieving 43.6dBm OIP3 实现43.6dBm OIP3的有源滤波器

2011 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2011-06-05 DOI: 10.1109/RFIC.2011.5940717

Helen Kim, M. Green, B. Miller, Andrew K. Bolstad, D. Santiago

引用次数: 4

Multiband mixed-signal vector modulator IC 多波段混合信号矢量调制器集成电路

2011 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2011-06-05 DOI: 10.1109/RFIC.2011.5940599

U. Mayer, M. Wickert, R. Eickhoff, F. Ellinger

引用次数: 11

A 60GHz digitally controlled RF beamforming array in 65nm CMOS with off-chip antennas 60GHz数字控制射频波束形成阵列在65nm CMOS与片外天线

2011 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2011-06-05 DOI: 10.1109/RFIC.2011.5940602

Saihua Lin, K. Ng, H. Wong, Kwai-Man Luk, S. Wong, A. Poon

引用次数: 37

Closed-loop spurious tone reduction for self-healing frequency synthesizers 闭环杂音减少自愈频率合成器

2011 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2011-06-05 DOI: 10.1109/RFIC.2011.5940704

F. Bohn, K. Dasgupta, A. Hajimiri

引用次数: 11

A phase-adjustable Delay-Locked Loop utilizing embedded phase interpolation 利用嵌入式相位插值的相位可调延迟锁相环

2011 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2011-06-05 DOI: 10.1109/RFIC.2011.5940657

Steven Callender, A. Niknejad

引用次数: 8

A multi-GHz 130ppm accuracy FLL for duty-cycled systems 用于占空比系统的多ghz 130ppm精度FLL

2011 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2011-06-05 DOI: 10.1109/RFIC.2011.5946283

X. Wang, B. Busze, J. Romme, R. Vinella, C. Zhou, K. Philips, H. de Groot

引用次数: 3

A 50% duty cycle wide-locking range divide-by-3 divider up to 6GHz 50%占空比宽锁范围除以3分频器，最高可达6GHz

2011 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2011-06-05 DOI: 10.1109/RFIC.2011.5940702

Chunyuan Zhou, Lei Zhang, Li Zhang, Yan Wang, Zhiping Yu, H. Qian

{"title":"A 50% duty cycle wide-locking range divide-by-3 divider up to 6GHz","authors":"Chunyuan Zhou, Lei Zhang, Li Zhang, Yan Wang, Zhiping Yu, H. Qian","doi":"10.1109/RFIC.2011.5940702","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940702","url":null,"abstract":"A synchronous 50% duty cycle divide-by-3 divider up to 6GHz is presented in this paper. The proposed architecture is composed of three identical delay cells with active inductor tank, which are injected by 3 input current with 120° phase splitting. The input current is provided by a double-balanced mixer mixing the outputs of the delay cells with the input clock signal. These cells are not stand alone, but coupled with each other. Thanks to the coupling and input current with 120° phase splitting, the outputs of the three cells are locked at the 1/3 input frequencies with 60°phase splitting, which means that the outputs are of an accurate 50% duty cycle. Injection behavior model is proposed for analysis, and some design guidelines are acquired here. This divider is fabricated in 0.18µm CMOS process and works with a nominal supply voltage of 1.8V. The measured results indicate that the locking range of this divider is 4GHz (from 2.5GHz to 6.5GHz) at an input power of 0dBm with about 4mW power dissipation. As high as 28dB second harmonic suppression of a single-ended output proves that this proposed divider realizes a true 50% duty cycle signal.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131953861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3