S. Andonova, D. Popovic, M. Kowalzik, M. Behrmann, J. Janneck
{"title":"Parallel coding of moving images using fractals","authors":"S. Andonova, D. Popovic, M. Kowalzik, M. Behrmann, J. Janneck","doi":"10.1109/ICAPP.1995.472287","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472287","url":null,"abstract":"A parallel fractal-based algorithm for predictive coding of a sequence of images is presented. The first frame in the sequence is fractal coded and transmitted. Each next frame is obtained as a motion compensated prediction by geometrically transforming the previous frame. The difference between the actual new frame and its prediction is fractal coded and transmitted to the receiver, in order to be used for the new frame reconstruction. A former-worker parallelization concept is used for parallel implementation of the computationally very extensive fractal-based video coding.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128418240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A parallel-computation model for nonlinear electromagnetic field analysis by harmonic balance finite element method","authors":"Junwei Lu, Yao Li, Chengzheng Sun, S. Yamada","doi":"10.1109/ICAPP.1995.472267","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472267","url":null,"abstract":"This paper presents a parallel computation model for the time-periodic nonlinear electromagnetic field analysis in the frequency domain using harmonic balance finite element method (HBFEM). The proposed model, different from the traditional HBFEM technique that requires large memory and long CPU time, divides the global system matrix into a number of matrices in the frequency domain. Each computation unit has exactly the same number of elements and unknown values. The work involved in calculating the element matrices is equal, therefore the load can be well-balanced and the maximum speed-up will be M times if M processors are available (M is the number of harmonics considered in the electromagnetic field). The model is well-suited to MIMD parallel computer or multiple computers connected by local area networks.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131280004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The design of a simulation system for distributed task scheduling algorithms","authors":"Jiannong Cao, M. Pole","doi":"10.1109/ICAPP.1995.472256","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472256","url":null,"abstract":"Task scheduling is an important part of any distributed computing environment. Distributed task scheduling algorithms aim at attaining increased performance of a distributed system by distributing the tasks of distributed programs onto the processors of the system. In designing a task scheduling mechanism, one needs to evaluate performance of task scheduling algorithms in order to decide among several algorithms or several versions of an algorithm. This paper describes the design of a general simulation system for distributed task scheduling algorithms. The design is highly modular and provides a system that can be configured and extended to simulate and evaluate different algorithms under different environments. The implementation of DisMimic, a prototype of the simulation system is also described. The framework described in this paper provides a basis of building toolbox to simplify the study of distributed task scheduling algorithms.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116937349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Jelly, P. R. Croll, I. Gorton, C. I. Birkinshaw
{"title":"Representation of client-server behaviour within parallel software designs","authors":"I. Jelly, P. R. Croll, I. Gorton, C. I. Birkinshaw","doi":"10.1109/ICAPP.1995.472182","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472182","url":null,"abstract":"Parallel software design techniques based on client-server process models have been proposed to support the development of deadlock free systems. Deadlock freedom can be guaranteed where no client-server cycles occur in process graphs. Hierarchical composition rules are presented which allow the designer more freedom, including the use of cycles at a higher level. The incorporation of these design rules into a software development methodology, PARSE, is described. When PARSE is used in this manner, it provides the parallel software engineer with a powerful software development framework and permits direct design verification.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116955282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Non-unimodular code generation for parallel machines","authors":"Jingling Xue","doi":"10.1109/ICAPP.1995.472184","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472184","url":null,"abstract":"Unimodular transformations have been used successfully in compiling programs for efficient execution on parallel machines. This paper discusses a number of code generation problems for which non-unimodular transformations are useful.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116969090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A distribution independent algorithm for the reduction to tridiagonal form using one-sided rotations","authors":"M. Hegland","doi":"10.1109/ICAPP.1995.472197","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472197","url":null,"abstract":"A scalable algorithm for the reduction to tridiagonal form of symmetric matrices is developed. It uses one-sided rotations instead of similarity transforms. This allows a data distribution independent implementation with low communication volume. Timings on the Fujitsu AP 1000 and VPP 500 show good performance.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121896995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A fault tolerant hierarchical interconnection network and its bandwidth analysis","authors":"S. Mahmud, L. T. Samaratunga","doi":"10.1109/ICAPP.1995.472261","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472261","url":null,"abstract":"A number of hierarchical interconnection networks (HINs) has been proposed in the literature which can be used for building large cluster-based multiprocessors. It is very desirable that a HIN must be fault tolerant, because even a single fault in the network can completely disconnect a large number of processors and memory modules from the rest of the system. As a result, the performance of the system will decrease significantly. In this paper, we have proposed a HIN which can work under faulty conditions but with a slight degradation in performance. We have also developed analytical models to determine the performance of the proposed fault tolerant HIN. The analytical models have been validated by simulation models.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115392341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multithreaded self-scheduling: application of multithreading on loop scheduling for distributed shared memory multiprocessor","authors":"K. P. Hung, N. Yung, Y. Cheung","doi":"10.1109/ICAPP.1995.472255","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472255","url":null,"abstract":"A new loop scheduling scheme called multithreaded self-scheduling (MSS) for distributed shared memory multiprocessor is proposed. Based on the principles of multithreading, MSS attempts to hide the remote memory access latencies by switching between multiple contexts of threads. Consequently, loops scheduled by using MSS can obtain better performance comparing to the single-thread approaches. In this paper a series of simulation results corresponding to various parameter changes are presented, which provides a measure of the effectiveness of MSS under different boundary conditions and suggests the ways for further improvements.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123655642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient one-sided Jacobi algorithms for singular value decomposition and the symmetric eigenproblem","authors":"B. Zhou, R. Brent, M. Kahn","doi":"10.1109/ICAPP.1995.472193","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472193","url":null,"abstract":"A method which uses one-sided Jacobi to solve singular valve decomposition and the symmetric eigen-valve problem in parallel is presented. We describe a parallel ring ordering for one-sided Jacobi computation. One distinctive feature of this ordering is that it can sort column norms in each sweep, which is very important to achieve fast convergence. Experimental results on both the Fujitsu AP1000 and the Fujitsu VPP500 are reported.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123264308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Memory design for row/column/diagonal access","authors":"A. Iconomidou, N. Sharma","doi":"10.1109/ICAPP.1995.472297","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472297","url":null,"abstract":"Summary form only given. Vectorizing involves parallel access to data elements from a random access memory (RAM). However, a single memory module of conventional design can access no more than one word during each cycle of the memory clock. One common solution is to partition the memory into multiple modules or memory banks with address interleaving, leading to a number of disadvantages and restrictions over vectorizing. A different approach is to design memory modules with build-in access ability to commonly used array partitions. In this paper, a new memory organization is proposed, in which words can be formed row-wise, column-wise or diagonally at the control of an external input. The behavioral and structural representation of this design have been defined.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129697481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}