{"title":"A fault tolerant hierarchical interconnection network and its bandwidth analysis","authors":"S. Mahmud, L. T. Samaratunga","doi":"10.1109/ICAPP.1995.472261","DOIUrl":null,"url":null,"abstract":"A number of hierarchical interconnection networks (HINs) has been proposed in the literature which can be used for building large cluster-based multiprocessors. It is very desirable that a HIN must be fault tolerant, because even a single fault in the network can completely disconnect a large number of processors and memory modules from the rest of the system. As a result, the performance of the system will decrease significantly. In this paper, we have proposed a HIN which can work under faulty conditions but with a slight degradation in performance. We have also developed analytical models to determine the performance of the proposed fault tolerant HIN. The analytical models have been validated by simulation models.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAPP.1995.472261","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A number of hierarchical interconnection networks (HINs) has been proposed in the literature which can be used for building large cluster-based multiprocessors. It is very desirable that a HIN must be fault tolerant, because even a single fault in the network can completely disconnect a large number of processors and memory modules from the rest of the system. As a result, the performance of the system will decrease significantly. In this paper, we have proposed a HIN which can work under faulty conditions but with a slight degradation in performance. We have also developed analytical models to determine the performance of the proposed fault tolerant HIN. The analytical models have been validated by simulation models.<>