2010 Ninth International Symposium on Parallel and Distributed Computing最新文献

Parallel Cycle Based Logic Simulation Using Graphics Processing Units 基于并行周期的图形处理单元逻辑仿真

2010 Ninth International Symposium on Parallel and Distributed Computing Pub Date : 2010-07-07 DOI: 10.1109/ISPDC.2010.26

A. Sen, Baris Aksanli, M. Bozkurt, Melih Mert

引用次数: 24

Exploiting the Power of GPUs for Multi-gigabit Wireless Baseband Processing 利用gpu的力量进行多千兆无线基带处理

2010 Ninth International Symposium on Parallel and Distributed Computing Pub Date : 2010-07-07 DOI: 10.1109/ISPDC.2010.19

T. Koçak, Nicholas Hinitt

引用次数: 2

Pretty Good Accuracy in Matrix Multiplication with GPUs 相当好的准确性在矩阵乘法与gpu

2010 Ninth International Symposium on Parallel and Distributed Computing Pub Date : 2010-07-07 DOI: 10.1109/ISPDC.2010.12

M. Badin, L. Bic, M. Dillencourt, A. Nicolau

引用次数: 1

Toward a Reliable Distributed Data Management System 一个可靠的分布式数据管理系统

2010 Ninth International Symposium on Parallel and Distributed Computing Pub Date : 2010-07-07 DOI: 10.1109/ISPDC.2010.15

Ismail Akturk, Xinqi Wang, T. Kosar

引用次数: 2

NQueens on CUDA: Optimization Issues CUDA上的NQueens:优化问题

2010 Ninth International Symposium on Parallel and Distributed Computing Pub Date : 2010-07-07 DOI: 10.1109/ISPDC.2010.22

Frank Feinbube, Bernhard Rabe, M. V. Löwis, A. Polze

引用次数: 21

Practical Uniform Peer Sampling under Churn 搅拌下的实用均匀对等抽样

2010 Ninth International Symposium on Parallel and Distributed Computing Pub Date : 2010-07-07 DOI: 10.1109/ISPDC.2010.25

R. Baldoni, M. Platania, Leonardo Querzoni, S. Scipioni

引用次数: 10

Improving Grid Fault Tolerance by Means of Global Behavior Modeling 用全局行为建模方法提高电网容错能力

2010 Ninth International Symposium on Parallel and Distributed Computing Pub Date : 2010-07-07 DOI: 10.1109/ISPDC.2010.20

Jesús Montes, Alberto Sánchez, María S. Pérez

引用次数: 5

A Method for Distributing Scheduling Heuristics Inside Service Oriented Environments Using a Nature-Inspired Approach 一种基于自然启发的面向服务环境中的分布式调度启发式方法

2010 Ninth International Symposium on Parallel and Distributed Computing Pub Date : 2010-07-07 DOI: 10.1109/ISPDC.2010.7

M. Frîncu

引用次数: 2

Performance Models for the Spike Banded Linear System Solver 尖峰带状线性系统求解器的性能模型

2010 Ninth International Symposium on Parallel and Distributed Computing Pub Date : 2010-07-07 DOI: 10.3233/SPR-2011-0316

M. Manguoglu, F. Saied, A. Sameh, A. Grama

{"title":"Performance Models for the Spike Banded Linear System Solver","authors":"M. Manguoglu, F. Saied, A. Sameh, A. Grama","doi":"10.3233/SPR-2011-0316","DOIUrl":"https://doi.org/10.3233/SPR-2011-0316","url":null,"abstract":"With availability of large-scale parallel platforms comprised of tens-of-thousands of processors and beyond, there is significant impetus for the development of scalable parallel sparse linear system solvers and preconditioners. An integral part of this design process, is the development of performance models capable of predicting performance and providing accurate cost models for the solvers and preconditioners. There has been some work in the past on characterizing performance of the iterative solvers themselves. In this paper, we investigate the problem of characterizing performance and scalability of banded preconditioners. Recent work has demonstrated the superior convergence properties and robustness of banded preconditioners, compared to state-of-the-art ILU family of preconditioners. Furthermore, when used in conjunction with efficient banded solvers, banded preconditioners are capable of significantly faster time-to solution. Our banded solver, the Truncated Spike algorithm is specifically designed for parallel performance and tolerance to deep memory hierarchies. Its regular structure is also highly amenable to accurate performance characterization. Using these characteristics, we derive the following results in this paper: (i) we develop parallel formulations of the Truncated Spike solver, (ii) we develop a highly accurate pseudo-analytical parallel performance model for our solver, (iii) we show excellent predication capabilities of our model – based on which we argue the high scalability of our solver. Our pseudo-analytical performance model is based on analytical performance characterization of each phase of our solver. These analytical models are then parameterized using actual runtime information on target platforms. An important consequence of our performance models is that they reveal underlying performance bottlenecks in both serial and parallel formulations. All of our results are validated on diverse heterogeneous multiclusters – platforms for which performance prediction is particularly challenging.","PeriodicalId":444451,"journal":{"name":"2010 Ninth International Symposium on Parallel and Distributed Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130152444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Resource-Aware Compiler Prefetching for Many-Cores 多核资源感知编译器预取

2010 Ninth International Symposium on Parallel and Distributed Computing Pub Date : 2010-07-07 DOI: 10.1109/ISPDC.2010.16

George C. Caragea, Alexandros Tzannes, Fuat Keceli, R. Barua, U. Vishkin

{"title":"Resource-Aware Compiler Prefetching for Many-Cores","authors":"George C. Caragea, Alexandros Tzannes, Fuat Keceli, R. Barua, U. Vishkin","doi":"10.1109/ISPDC.2010.16","DOIUrl":"https://doi.org/10.1109/ISPDC.2010.16","url":null,"abstract":"Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi-and many-cores with shared parallel caches further increase MLP demand. Current cache hierarchies however have been unable to keep up with this trend, with modern designs allowing only 4-16 concurrent cache misses. This disconnect is exacerbated by recent highly parallel architectures (e.g. GPUs) where power and area per-core budget favor lighter cores with less resources. Support for hardware and software prefetch increase MLP pressure since these techniques overlap multiple memory requests with existing computation. In this paper, we propose and evaluate a novel Resource-Aware Prefetching (RAP) compiler algorithm that is aware of the number of simultaneous prefetches supported, and optimized for the same. We show that in situations where not enough resources are available to issue prefetch instructions for all references in a loop, it is more beneficial to decrease the prefetch distance and prefetch for as many references as possible, rather than use a fixed prefetched distance and skip prefetching for some references, as in current approaches. We implemented our algorithm in a GCC-derived compiler and evaluated its performance using an emerging fine-grained many-core architecture. Our results show that the RAP algorithm outperforms a well-known loop prefetching algorithm by up to 40.15% and the state-of-the art GCC implementation by up to 34.79%. Moreover, we compare the RAP algorithm with a simple hardware prefetching mechanism, and show improvements of up to 24.61%.","PeriodicalId":444451,"journal":{"name":"2010 Ninth International Symposium on Parallel and Distributed Computing","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126355906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16