{"title":"Hand Gesture Recognition System in the Complex Background for Edge Computing Devices","authors":"Chakkapalli Manikanta Suryateja, Srinivas Boppu, Linga Reddy Cenkeramaddi, Barathram Ramkumar","doi":"10.1109/iSES54909.2022.00016","DOIUrl":"https://doi.org/10.1109/iSES54909.2022.00016","url":null,"abstract":"Hand gesture recognition offers a wide range of contactless applications. Some applications include designing a sign language recognition system for communicating with people having disabilities, health-care, automobiles, security, etc. For deaf and hard-of-hearing people, sign language recognition is a game-changer and has been studied for years. Unfortunately, each study has its limitations and cannot be used commercially. Some inves-tigations have shown that detecting sign language is possible, but commercialization is prohibitively expensive. This paper investi-gates a robust system to implement hand gesture recognition in a complex background. To test the hand gesture recognition system design, we developed an American sign language recognition for the letters A-J in a complex environment. The MediaPipe Hands framework, used in the developed system, helps successfully detect the hand landmark positions. The machine learning techniques are built on top of the obtained hand landmark positions. The developed system achieves 98.1% accuracy in gesture recognition with an inference time of around 50 ms. Subsequently, the system is successfully ported to Raspberry Pi 4 and NVIDIA's Jetson AGX Xavier and tested.","PeriodicalId":438143,"journal":{"name":"2022 IEEE International Symposium on Smart Electronic Systems (iSES)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116662072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Process-Voltage-Temperature insensitive hybrid Voltage controlled ring oscillator for Biomedical IoT node","authors":"M. N. K. Reddy, S. Patri","doi":"10.1109/iSES54909.2022.00104","DOIUrl":"https://doi.org/10.1109/iSES54909.2022.00104","url":null,"abstract":"This work presents a PVT insensitive ring oscillator (RO) for IoT applications. A five-stage RO is designed by integrating diverse delay cells having contradictory temperature characteristics, complementary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) delay cells to reduce the temperature coefficient. In addition, auxiliary circuit is employed to compensate for process and supply variations. The RO implemented with a 180 nm standard CMOS process reliably produces a 6.8 MHz reference frequency with a temperature drift of 0.9 % at the supply voltage of 1.2 V. Also, it operates at a low power dissipation of 362 µW with an compact area of 4080 µm2.","PeriodicalId":438143,"journal":{"name":"2022 IEEE International Symposium on Smart Electronic Systems (iSES)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121033522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Seema G. Aarella, S. Mohanty, E. Kougianos, Deepak Puthal
{"title":"PUF-based Authentication Scheme for Edge Data Centers in Collaborative Edge Computing","authors":"Seema G. Aarella, S. Mohanty, E. Kougianos, Deepak Puthal","doi":"10.1109/iSES54909.2022.00094","DOIUrl":"https://doi.org/10.1109/iSES54909.2022.00094","url":null,"abstract":"Fog computing gained importance when the re-quired infrastructure became more decentralized. The difference between Fog and Edge computing is that the former has nodes between the cloud and edge devices. In a way both fog and edge computing bring data processing closer to end-user devices. Edge Data Centers (EDCs) are employed to bring the processing power closer to the end-user to address latency in real-time applications, bandwidth, battery life constraints, as well as data privacy and safety. Edge Data centers are employed in collaborative edge computing environments across network edges, and they deliver uninterrupted processing through load balancing, where an overloaded Edge Data Center can off-load its task to the next available EDC. Authenticating EDCs is one of the challenges in collaborative edge computing environment where load balancing is applied. Physical Unclonable Functions (PUFs) are lightweight innovative primitives that are used for authentication and secure key storage. This work proposes a novel authentication scheme for EDCs using virtual Physical Unclonable Functions as a secure oPtion.","PeriodicalId":438143,"journal":{"name":"2022 IEEE International Symposium on Smart Electronic Systems (iSES)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123743107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"EEG based mental task classification using arithmetic operations","authors":"Privadarsini Samal, Mohammad Farukh Hashmi","doi":"10.1109/iSES54909.2022.00112","DOIUrl":"https://doi.org/10.1109/iSES54909.2022.00112","url":null,"abstract":"The human brain is exposed to a variety of positive and negative emotions, such as stress, happiness, frustration, and attention, while completing any task. Techniques for brain-computer interface (BCI) can be used to study and identify these emotions. The most widely used neuroimaging technique for the examination of brain activity is the Electroencephalogram (EEG), which is affordable, reliable, and non-invasive. Here, the EEG signal pattern during the introduction of a mental task is investigated. In the study, the dataset was taken from PHYSIONET, named as EEG during mental arithmetic tasks. Data of ten healthy volunteers was taken among 36 participants in two different modes-rest and mental task-with a sample frequency of 500 Hz. Overall, all, 11 frequency domain features were examined in this work, including power band features, band power ratios, and relative powers. Additionally, two wavelet features-spectral entropy and Shannon entropy-were added to the feature set. From time domain features, mean, standard deviation and variation features were also extracted. Six Classifiers were used and among them neural networks provided highest accuracy of 98.8%.","PeriodicalId":438143,"journal":{"name":"2022 IEEE International Symposium on Smart Electronic Systems (iSES)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125351899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. C. Sethuraman, Aditya Mitra, Gautam Galada, Anisha Ghosh, Anitha Subramanian
{"title":"Metakey: A Novel and Seamless Passwordless Multifactor Authentication for Metaverse","authors":"S. C. Sethuraman, Aditya Mitra, Gautam Galada, Anisha Ghosh, Anitha Subramanian","doi":"10.1109/iSES54909.2022.00148","DOIUrl":"https://doi.org/10.1109/iSES54909.2022.00148","url":null,"abstract":"The Metaverse offers a collection of virtual reality “worlds” for interaction, communication, teamwork, gaming, entertainment, and other purposes. The concept of the Meta-verse and its application encourage the development of human civilization across time. In contrast to communications via phone conversations or meetings, it removes the obstacles to distant communication and increases its dependability for everyone because each entity will be authenticated on a virtual platform. As a result, the spam callers or attackers stand out from the groups of permitted persons. Multilingual communication makes language barriers both locally and internationally more common. Additionally, the idea of digital assets is introduced. This research presents a novel authentication and identity management frame-work called MetaKey, which aims at securing one's digital assets and digital identity. The proposed system provides multi-factor, Passwordless authentication with the high security of biometric recognition and cryptographic algorithms.","PeriodicalId":438143,"journal":{"name":"2022 IEEE International Symposium on Smart Electronic Systems (iSES)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125523476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and FPGA Implementation of the LUT based Sigmoid Function for DNN Applications","authors":"Revathi Pogiri, S. Ari, K. Mahapatra","doi":"10.1109/iSES54909.2022.00090","DOIUrl":"https://doi.org/10.1109/iSES54909.2022.00090","url":null,"abstract":"Nowadays deep learning algorithms are became popular in the field of biomedical applications for automatic classification and detection problems. There are multiple issues in implementing these algorithms on digital platform. The major issue is it requires a dedicated hardware to meet the low power requirements in real-time. Hence, the low power hardware accelerators for deep neural network (DNN) classifiers is developed in this work to cope the above issue. In a DNN, activation function is important in feature classification. In this work, an area efficient digital architecture for evaluating the sigmoid function is also proposed and its resource requirements reported. The proposed architecture took the advantage of symmetry of sigmoid function and save 50% of the storage area. The performance of the proposed architecture is assessed by separately employing the proposed sigmoid and theoretical sigmoid blocks in a simple Convolution Neural Network (CNN) and observed that the model with quantized processing achieved the accuracy close to the model performance with traditional sigmoid block.","PeriodicalId":438143,"journal":{"name":"2022 IEEE International Symposium on Smart Electronic Systems (iSES)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126737841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Message from the Technical Program Chairs: iSES 2022","authors":"","doi":"10.1109/ises54909.2022.00006","DOIUrl":"https://doi.org/10.1109/ises54909.2022.00006","url":null,"abstract":"","PeriodicalId":438143,"journal":{"name":"2022 IEEE International Symposium on Smart Electronic Systems (iSES)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126826749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Broadband MIMO Array with Gap Coupling For 5G Applications","authors":"Srivalli Gundala, Vssn SrinivasaBaba, Adepu Vijaya","doi":"10.1109/iSES54909.2022.00107","DOIUrl":"https://doi.org/10.1109/iSES54909.2022.00107","url":null,"abstract":"A Multiple Input Multiple Output (MIMO) array was designed using a Broadband three-patch gap antenna which has both electric and magnetic elements to couple. A step design is implemented between the elements for Electromagnetic coupling. A MIMO Antenna of four element with a gap is designed at 3.75 GHz. It has the advantages of wideband and multiband capabilities, lower in weight, less volume with thinner dimensions. Communication through 5G Applications is the state of art Technology in which the proposed antenna is most suitable. The compact multiple input multiple output four element array is designed at a frequency of 3.75 GHz. The designed MIMO array has good impedance matching and high isolation between channels. A Comparison with different substrates is done for Optimization. The three layered design in which air is considered as one of the substrates gives very good performance characteristics.","PeriodicalId":438143,"journal":{"name":"2022 IEEE International Symposium on Smart Electronic Systems (iSES)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122475416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Top-down Approach to Solving Speaker Diarization Errors in diaLogic System","authors":"Ryan Duke, A. Doboli","doi":"10.1109/iSES54909.2022.00051","DOIUrl":"https://doi.org/10.1109/iSES54909.2022.00051","url":null,"abstract":"Speaker diarization, which separates continuous speech signals into utterances associated to different speakers, is critical to any environment that supports team collaboration using models based on data extracted from speech. However, the occurring diarization errors are hard to reduce only through better processing. This paper proposes top-down error correction based on Bayesian prediction about the most likely author of an utterance. Experiments studied the effectiveness of the method.","PeriodicalId":438143,"journal":{"name":"2022 IEEE International Symposium on Smart Electronic Systems (iSES)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114570607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance Analysis of Dual Material Graded Channel Cylindrical Gate All Around (DMGC CGAA) FET with Source/Drain Underlap","authors":"Praveen Kumar Mudidhe, B. Nistala","doi":"10.1109/iSES54909.2022.00068","DOIUrl":"https://doi.org/10.1109/iSES54909.2022.00068","url":null,"abstract":"In this paper the effect of underlap on Dual material graded channel cylindrical gate all around FET (DMGC CGAA FET) has been investigated. Due to improved gate electrostatic control, multigate structures have greater short channel control than typical bulk devices. The DMGC CGAA FET is a potential candidate among the multi gate devices because of its ease of manufacture. The inclusion of gate underlap in the proposed device improves the short channel immunity. To further enhance the device performance different types of spacers are incorpo-rated in the underlap regions. The underlap length $(L_{un})$ was optimized at 4.5 nm for the proposed device. Simulation results shows that there is an improvement in the switching ratio $(frac{I_{on}}{I_{off}})$, subthreshold swing (SS) and other SCEs. The DC and Analog/RF performance was investigated with different types of spacers and observed that HfO2 results the better subthreshold performance compared with other spacers. Sentaurus TCAD simulator was used to extract the simulation results and to calibrate the device with experimental data.","PeriodicalId":438143,"journal":{"name":"2022 IEEE International Symposium on Smart Electronic Systems (iSES)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121664997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}