发布求助
文献互助 智能选刊 最新文献

2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)最新文献

筛选
英文 中文
Attention-Based Secure Feature Extraction in Near Sensor Processing: Work-in-Progress 近传感器处理中基于注意力的安全特征提取:正在研究中
2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2020-09-20 DOI: 10.1109/CODESISSS51650.2020.9244036
Pankaj Bhowmik, Md Jubaer Hossain Pantho, S. Saha, C. Bobda
{"title":"Attention-Based Secure Feature Extraction in Near Sensor Processing: Work-in-Progress","authors":"Pankaj Bhowmik, Md Jubaer Hossain Pantho, S. Saha, C. Bobda","doi":"10.1109/CODESISSS51650.2020.9244036","DOIUrl":"https://doi.org/10.1109/CODESISSS51650.2020.9244036","url":null,"abstract":"This paper presents a secure hardware architecture of an image sensor to accelerate feature extraction using region-level parallelism. For each logical region, the design includes a region processing unit (RPU) with an attention module (AM). The AM activates the processing in the RPU if there are no spatiotemporal redundancies. It reduces power consumption and data volume by utilizing the concepts of predictive coding. Also, every RPU has a crypto-core driven by the AM to withstand against adversaries. Simulation results show we can save 89.70% power with a significant speedup.","PeriodicalId":437802,"journal":{"name":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115123244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An ESL Methodology for HW/SW Co-Design of Monitorable Embedded Systems: the “Design for Monitorability” Project - Work-in-Progress 可监控嵌入式系统的硬件/软件协同设计的ESL方法:“可监控性设计”项目-正在进行中
2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2020-09-20 DOI: 10.1109/CODESISSS51650.2020.9244025
G. Valente, T. D. Mascio, L. Pomante, Vincenzo Stoico
{"title":"An ESL Methodology for HW/SW Co-Design of Monitorable Embedded Systems: the “Design for Monitorability” Project - Work-in-Progress","authors":"G. Valente, T. D. Mascio, L. Pomante, Vincenzo Stoico","doi":"10.1109/CODESISSS51650.2020.9244025","DOIUrl":"https://doi.org/10.1109/CODESISSS51650.2020.9244025","url":null,"abstract":"This paper proposes an Electronic System-Level (ESL) Methodology for HW/SW Co-Design of Monitorable Embedded Systems. In particular, this paper aims to define an innovative topic called Design for Monitorability (DfM). DfM exploits ESL HW/SW co-design techniques to satisfy Monitorability Requirements (M_REQs) by considering them since the initial steps of the HW/SW co-design flow as additional ones. DfM has the final goal of suggesting to the designer an On-Chip Monitoring System (OCMS) able to satisfy M _ REQs., to be integrated in the final system (i.e., possibly heterogeneous and/or parallel SoCs) while still respecting the other possible nonfunctional requirements imposed to the system implementation (e.g., execution time, area/resource utilization, energy consumption, etc.). The description of the motivations and the main concepts behind the proposed methodology represent the core of the paper.","PeriodicalId":437802,"journal":{"name":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126655411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Techniques for Design Analysis and Modification Based on ASAP Model: Work-in-Progress 基于ASAP模型的设计分析与修改技术:正在研究中
2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2020-09-20 DOI: 10.1109/CODESISSS51650.2020.9244023
Ke Du, S. Domas, M. Lenczner
{"title":"Techniques for Design Analysis and Modification Based on ASAP Model: Work-in-Progress","authors":"Ke Du, S. Domas, M. Lenczner","doi":"10.1109/CODESISSS51650.2020.9244023","DOIUrl":"https://doi.org/10.1109/CODESISSS51650.2020.9244023","url":null,"abstract":"In the domain of model-based design, the main challenge is to provide a model with a set of conditions and algorithms to ensure that the designed system produces correct results. A dataflow based model called Actors with Stretchable Access Patterns (ASAP) has been recently proposed, which takes the behavior of functional blocks on real architectures, especially FPGAs, into account. In this work, we present the framework of techniques to analyze the correctness of designs based on the ASAP model and to determine a set of modifications that must be applied to faulty cases to ensure the conformance of all actors. The principles are illustrated by a realistic application.","PeriodicalId":437802,"journal":{"name":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"503 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115941196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress 抵御对抗性攻击的热图感知低成本设计:正在进行的工作
2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2020-09-20 DOI: 10.1109/CODESISSS51650.2020.9244017
Zhiyuan He, Wei Jiang, Jinyu Zhan, Xupeng Wang, Xiangyu Wen
{"title":"Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress","authors":"Zhiyuan He, Wei Jiang, Jinyu Zhan, Xupeng Wang, Xiangyu Wen","doi":"10.1109/CODESISSS51650.2020.9244017","DOIUrl":"https://doi.org/10.1109/CODESISSS51650.2020.9244017","url":null,"abstract":"It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promising result, which however suffers from a high computation cost. In this paper, we design a new heatmap-aware method to defend adversarial attacks, leading to a significant decrease in the time cost. To be specific, we compute the classification importance from each part of the input to obtain the heatmap of the data, and the key areas of classification are extracted according to the heatmap. A series of transformations are applied to the key areas of the classification, which reduces the amount of data to be processed and thus reduces the time cost. A set of preliminary experiments are conducted to testify the effectiveness of the proposed approach.","PeriodicalId":437802,"journal":{"name":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114471267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy for Blockchain Storage Systems: Work-in-Progress 元链:区块链存储系统的用户感知跨层空间分配策略:正在进行中
2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2020-09-20 DOI: 10.1109/CODESISSS51650.2020.9244016
J. Liao, Zhengda Li, Yi Wang
{"title":"Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy for Blockchain Storage Systems: Work-in-Progress","authors":"J. Liao, Zhengda Li, Yi Wang","doi":"10.1109/CODESISSS51650.2020.9244016","DOIUrl":"https://doi.org/10.1109/CODESISSS51650.2020.9244016","url":null,"abstract":"Current LSM-Tree-based blockchain storage system will assign the data from multiple system users to the same disk drive. This will lead to the inefficient usage of physical spaces in disk and cause extra compaction operations for LSM - Tree. This paper presents Meta-Chain, a user-aware cross-layer space allocation strategy for blockchain storage systems. As a cross-layer design, Meta-Chain redesigns the organization of LSM - Tree and utilizes the rich functionalities provided by open-channel SSD. Experimental results show that Meta-Chain can effectively reduce write amplification and extend the lifetime of SSD in comparison with representative schemes.","PeriodicalId":437802,"journal":{"name":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130198612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Formal Verification of GCSE in the Scheduling of High-level Synthesis: Work-in-Progress 高级综合调度中GCSE的正式验证:正在进行中
2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2020-09-20 DOI: 10.1109/CODESISSS51650.2020.9244039
Jian Hu, Yongyang Hu, Long Yu, Wentao Wang, Haitao Yang, Yun Kang, Jie Cheng
{"title":"Formal Verification of GCSE in the Scheduling of High-level Synthesis: Work-in-Progress","authors":"Jian Hu, Yongyang Hu, Long Yu, Wentao Wang, Haitao Yang, Yun Kang, Jie Cheng","doi":"10.1109/CODESISSS51650.2020.9244039","DOIUrl":"https://doi.org/10.1109/CODESISSS51650.2020.9244039","url":null,"abstract":"High-level synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/SystemC) into a register-transfer level (RTL) implementation. However, an error may exist in the RTL implementation from the compiler in the high-level synthesis due to the complex and error prone compiling process. Global common subexpression elimination (GCSE) is a commonly used code motion technique in the scheduling of high-level synthesis. In this paper, we present an equivalence checking method to verify GCSE in the scheduling of high-level synthesis by enhancing the path equivalence criteria. The initial experimental results demonstrate our method can indeed verify the GCSE which has not been properly addressed in the past.","PeriodicalId":437802,"journal":{"name":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132438282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Energy-aware Spiking Neural Network Hardware Mapping based on Particle Swarm Optimization and Genetic Algorithm 基于粒子群优化和遗传算法的能量感知峰值神经网络硬件映射
2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2020-09-20 DOI: 10.1109/CODESISSS51650.2020.9244037
Junxiu Liu, Xingyue Huang, Dong Jiang, Yuling Luo
{"title":"An Energy-aware Spiking Neural Network Hardware Mapping based on Particle Swarm Optimization and Genetic Algorithm","authors":"Junxiu Liu, Xingyue Huang, Dong Jiang, Yuling Luo","doi":"10.1109/CODESISSS51650.2020.9244037","DOIUrl":"https://doi.org/10.1109/CODESISSS51650.2020.9244037","url":null,"abstract":"Spiking Neuron Network (SNN) is a biological neural network model which shows great capability in the time series data processing and pattern recognition etc. according to the recent research. It has been implemented in hardware system with a good scalability, where the Networks-on-Chip (NoC) interconnection strategy is widely used for the data communications between the neurons. The mapping between a SNN and a NoC hardware system is one of the challenge for the development of the hardware SNNs. In this paper, a hybrid Particle Swarm Optimization (PSO) algorithm for hardware SNN mapping is proposed with the object of minimizing the energy consumption. Compared to the conventional PSO, it can search the mapping solutions through three directions which can speed up the finding. In the meantime, the Genetic Algorithm (GA) is combined to provide the mutation operation to avoid converging to the local optimum. A typical hardware SNN is used as the testbench and results show that an effective hardware SNN mapping is obtained with a low energy consumption, and local optimum is avoided compared to other approaches.","PeriodicalId":437802,"journal":{"name":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122029560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
GraphPage: RDF Graph in SSD Pages: Work-in-Progress GraphPage: SSD页面中的RDF图:正在进行中
2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2020-09-20 DOI: 10.1109/CODESISSS51650.2020.9244042
Guohua Yan, Renhai Chen, Zhiyong Feng
{"title":"GraphPage: RDF Graph in SSD Pages: Work-in-Progress","authors":"Guohua Yan, Renhai Chen, Zhiyong Feng","doi":"10.1109/CODESISSS51650.2020.9244042","DOIUrl":"https://doi.org/10.1109/CODESISSS51650.2020.9244042","url":null,"abstract":"SSD has been widely deployed in data centers to provide low access latency with high throughput for large-scale RDF storage system. When performing data query on SSDs, the RDF -based graph data may be sequentially read multiple times due to the semantic gap between the graph and SSD structures. In this paper, we propose a scheme called GraphPage to bridge the semantic gap between RDF graph and SSD. GraphPage partitions the RDF graph into small graphs and directly maps these small graphs into the flash pages. To achieve this, we first expose the internal page organization by redesigning an SSD. By exploring the page-level graph store, we can efficiently reduce the page access times inside SSDs, thus significantly enhancing the query efficiency. We conduct experiments on a real hardware platform. Extensive experiments on synthetic and real datasets show that the proposed strategy improves the performance of data query by more than two times.","PeriodicalId":437802,"journal":{"name":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122122303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress 修复:降低峰值温度同时最大限度地提高近似实时计算精度的策略:正在进行的工作
2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2020-09-20 DOI: 10.1109/CODESISSS51650.2020.9244040
Shounak Chakraborty, S. Saha, Magnus Själander, K. Mcdonald-Maier
{"title":"RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress","authors":"Shounak Chakraborty, S. Saha, Magnus Själander, K. Mcdonald-Maier","doi":"10.1109/CODESISSS51650.2020.9244040","DOIUrl":"https://doi.org/10.1109/CODESISSS51650.2020.9244040","url":null,"abstract":"Improving accuracy in approximate real-time computing without violating thermal-energy constraints of the underlying hardware is a challenging problem. The execution of approximate real-time tasks can individually be bifurcated into two components: (i) execution of the mandatory part of the task to obtain a result of acceptable quality, followed by (ii) partial/complete execution of the optional part, which refines the initially obtained result, to increase the accuracy without violating the temporal-deadline. This paper introduces RePAiR, a novel task-allocation strategy for approximate real-time applications, combined with fine-grained DVFS and on-line task migration of the cores and power-gating of the last level cache, to reduce chip-temperature while respecting both deadline and thermal constraints. Furthermore, gained thermal benefits can be traded against system-level accuracy by extending the execution-time of the optional part.","PeriodicalId":437802,"journal":{"name":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127936691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress
2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2020-09-20 DOI: 10.1109/CODESISSS51650.2020.9244038
Alessio Colucci, Alberto Marchisio, Beatrice Bussolino, Voitech Mrazek, M. Martina, G. Masera, M. Shafique
{"title":"A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress","authors":"Alessio Colucci, Alberto Marchisio, Beatrice Bussolino, Voitech Mrazek, M. Martina, G. Masera, M. Shafique","doi":"10.1109/CODESISSS51650.2020.9244038","DOIUrl":"https://doi.org/10.1109/CODESISSS51650.2020.9244038","url":null,"abstract":"The Capsule Networks (CapsNets) is an advanced form of Convolutional Neural Network (CNN), capable of learning spatial relations and being invariant to transformations. CapsNets requires complex matrix operations which current accelerators are not optimized for, concerning both training and inference passes. Current state-of-the-art simulators and design space exploration (DSE) tools for DNN hardware neglect the modeling of training operations, while requiring long exploration times that slow down the complete design flow. These impediments restrict the real-world applications of CapsNets (e.g., autonomous driving and robotics) as well as the further development of DNNs in life-long learning scenarios that require training on low-power embedded devices. Towards this, we present XploreDL, a novel framework to perform fast yet high-fidelity DSE for both inference and training accelerators, supporting both CNNs and CapsNets operations. XploreDL enables a resource-efficient DSE for accelerators, focusing on power, area, and latency, highlighting Pareto-optimal solutions which can be a green-lit to expedite the design flow. XploreDL can reach the same fidelity as ARM's SCALE-sim, while providing 600x speedup and having a 50x lower memory-footprint. Preliminary results with a deep CapsNet model on MNIST for training accelerators show promising Pareto-optimal architectures with up to 0.4 TOPS/squared-mm and 800 fJ/op efficiency. With inference accelerators for AlexNet the Pareto-optimal solutions reach up to 1.8 TOPS/squared-mm and 200 fJ/op efficiency.","PeriodicalId":437802,"journal":{"name":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129950218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信