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2008 9th International Conference on Solid-State and Integrated-Circuit Technology最新文献

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A survey of RLCK reduction and simulation methods by fast truncated balanced realization 快速截断平衡实现的RLCK降噪及仿真方法综述
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4735035
Boyuan Yan, Hai Wang, S.X.-D. Tan
{"title":"A survey of RLCK reduction and simulation methods by fast truncated balanced realization","authors":"Boyuan Yan, Hai Wang, S.X.-D. Tan","doi":"10.1109/ICSICT.2008.4735035","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735035","url":null,"abstract":"Model order reduction by truncated balanced realization (TBR) is better than Krylov subspace methods to achieve smaller models with global error control. TBR projects a system onto the dominant invariant subspace in terms of both controllability and observability measured by their gramians. However, to obtain two gramians, two Lyapunov equations have to be solved and its high computation costs involved limit its application to only small circuits. To mitigate this problem, several methods are proposed to obtain the approximated dominant subspace of the gramian (or gramian product). In this paper, we survey several recently proposed fast TBR methods by gramian approximation techniques for the model order reduction and simulation of RLCK circuits. We present the pros and cons of each method and compare them on some large RLCK circuits.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114615377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Yield analysis methods in 65nm technology Development 65纳米工艺中良率分析方法的开发
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734755
S. Wei, E. Liu, L. Wei
{"title":"Yield analysis methods in 65nm technology Development","authors":"S. Wei, E. Liu, L. Wei","doi":"10.1109/ICSICT.2008.4734755","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734755","url":null,"abstract":"For the new technology development, normal yield improvement methods useful to production are not enough. In the early phases, without yield signature, many systematic issues can not be captured by WAT or inline defect inspections. We need to create new analysis methods based on the technology development different phases. At the same time, multiple issues usually mix together and are not easy to be distinguished. So the selection of test chips, EFA (electrical failure analysis), PFA (physical failure analysis) and DFA (data failure analysis) methods become more important. This paper mainly focuses on the yield improvement methodologies in 65 nm three phases at foundry.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114808506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low complexity channel estimation and tracking method for high speed mobile communication systems 高速移动通信系统的低复杂度信道估计与跟踪方法
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734862
Meng Cai, Ke-feng Zhang, X. Zou
{"title":"Low complexity channel estimation and tracking method for high speed mobile communication systems","authors":"Meng Cai, Ke-feng Zhang, X. Zou","doi":"10.1109/ICSICT.2008.4734862","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734862","url":null,"abstract":"In the paper, the channel estimation and tracking method for mobile orthogonal frequency division multiplexing (OFDM) systems is developed. The channel estimation method is based on a frequency domain finite impulse response (FIR) filter, while the tracking method is based on a Kalman filter. The proposed method could effectively track the time-variant of the channel with Doppler delay spread. Moreover, the method achieves good performance with low complexity, which makes the hardware implementation facilitated.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124461256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High speed CMOS output stage for integrated DC-DC converters 用于集成DC-DC转换器的高速CMOS输出级
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734950
Wai Tung, Marian Changl, Abraham Yo, Jiri Langer, Tim Hedquise, Helmut Schweiss
{"title":"High speed CMOS output stage for integrated DC-DC converters","authors":"Wai Tung, Marian Changl, Abraham Yo, Jiri Langer, Tim Hedquise, Helmut Schweiss","doi":"10.1109/ICSICT.2008.4734950","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734950","url":null,"abstract":"A Hybrid Waffle layout technique is introduced for the design of CMOS power transistors in integrated low voltage DC-DC converters. Comparing with conventional multi-finger layout scheme, the Hybrid Waffle layout scheme allows optimized trade-off between device on-resistance and metal interconnect resistance to minimize overall on-resistance. Interestingly, the reduced channel width per unit area also leads to lower gate capacitance and faster switching speed. This paper presents a prototype DC-DC converter IC that contains integrated gate drivers, protection circuits and CMOS output transistors. Implemented in a standard 0.25 ¿m CMOS, this IC can be switched at 12.5 MHz with output current rated at 800 mA with input voltage of up to 4.2 V. Peak power efficiency of 85% was observed at 100 mA. Die size is 1.1 × 1.5 mm2.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127716017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
REBULF technology for bulk silicon and SOI lateral high-voltage devices 用于大块硅和SOI横向高压器件的REBULF技术
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734497
Bo Zhang, Jianbing Cheng, M. Qiao, Zhaoji Li
{"title":"REBULF technology for bulk silicon and SOI lateral high-voltage devices","authors":"Bo Zhang, Jianbing Cheng, M. Qiao, Zhaoji Li","doi":"10.1109/ICSICT.2008.4734497","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734497","url":null,"abstract":"Reduced Bulk Field (REBULF) technology is used in the design of lateral power devices to improve breakdown voltage. Since this technology was firstly presented in 2006, this technology has gained widespread attention amongst researchers and has shown to offer good performance in a variety of application domains, especially in bulk silicon and SOI. This paper aims to offer a compendious and timely review of the technology and some work of our lab on the application of this technology in bulk silicon and SOI.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122212409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Influence of surface orientation on electrical characteristics in MOSFETs with slightly tilted off-axis channel 表面取向对微倾斜离轴沟道mosfet电特性的影响
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734489
H. Momose
{"title":"Influence of surface orientation on electrical characteristics in MOSFETs with slightly tilted off-axis channel","authors":"H. Momose","doi":"10.1109/ICSICT.2008.4734489","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734489","url":null,"abstract":"Si surface properties and electrical characteristics in n- and p-MOSFETs with 2 - 6 degree tilted off-axis (110) channel were reported. The transconductance of p-MOSFET with off-axis channel was significantly degraded compared with that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved compared with that of normal channel. The changes were larger than those observed in slightly off-axis (100) samples. The gate leakage current and 1/f noise in (110) samples were also sensitive to off-axis angle.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122276745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel mechanical switch devices for reconfigurable IC applications 用于可重构集成电路应用的新型机械开关器件
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734974
W. Wang
{"title":"Novel mechanical switch devices for reconfigurable IC applications","authors":"W. Wang","doi":"10.1109/ICSICT.2008.4734974","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734974","url":null,"abstract":"In this paper, the novel mechanical switch device: suspended-gate FET is applied to FPGA development. This device offers almost an ideal subthreshold swing and a hysteretic resistance switching, opening opportunities for low-power applications. The proposed device can be used as the building block of programmable elements and memory of an FPGA. Based on this device, the proposed FPGA architecture, SG-FPGA, can maintain the baseline FPGA architecture and significantly reduce the size and power consumption of the memory and routing elements. The simulation results demonstrate that the application of SG-FET to FPGA chips can provide at least 3X-5X performance gains in terms of density and power.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115893799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimal clock overlapping of four-phase Dickson charge pump for power efficiency improvement 提高四相电荷泵功率效率的最佳时钟重叠
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734914
Kai Yu, X. Zou, Guoyi Yu, Sizhen Li
{"title":"Optimal clock overlapping of four-phase Dickson charge pump for power efficiency improvement","authors":"Kai Yu, X. Zou, Guoyi Yu, Sizhen Li","doi":"10.1109/ICSICT.2008.4734914","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734914","url":null,"abstract":"This paper presents a compact power efficiency model to be applied in the analysis and design of clock overlapping of four-phase Dickson charge pump. The hands in equations on the optimal clock overlapping are concluded. Based on 0.25 um CMOS technology, the proposed model is consistent with the simulation result. Both simulation and model validate the optimal clock overlapping range attains better power efficiency when compare conventional designs.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131457824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Three-dimensional impedance engineering for mixed-signal system-on-chip applications 混合信号片上系统应用的三维阻抗工程
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734826
K. Chong, Yahong Xie
{"title":"Three-dimensional impedance engineering for mixed-signal system-on-chip applications","authors":"K. Chong, Yahong Xie","doi":"10.1109/ICSICT.2008.4734826","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734826","url":null,"abstract":"We describe a novel approach for three-dimensional substrate impedance engineering using p-/p+ epi substrate for mixed-signal SoC applications. Highly doped substrate with a thin epitaxial layer is used to prevent latch-up at tight design rules in high performance digital CMOS for beyond 40 GHz applications. Metal vias extending from the chip surface to the p+ substrate are used as Faraday cage for EM wave shielding as well as ¿true ground¿ contacts. Self-limiting semi-insulating micro-PS regions are inserted into selected regions of Si substrates from the backside of the wafer. On-chip inductors are situated above the semi-insulating micro-PS regions allowing for greatly increased Q and fr. Bond pads on micro-PS regions increase the bond pad resonant frequency of up to 56.2 GHz and increase crosstalk isolation between bond pads. These technologies require minimum intrusion to conventional Si CMOS processing, making them practical and yet effective new technologies that offer outstanding improvements with regard to the performance of mixed-signal SoCs. It is an enabling factor for Si ICs to directly challenge the compound semiconductor technologies.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132006791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
System design considerations of highly-integrated UHF RFID reader transceiver RF front-end 高集成度超高频RFID读写器收发射频前端的系统设计考虑
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734855
Jingchao Wang, B. Chi, Xuguang Sun, Tongqiang Gao, Chun Zhang, Zhihua Wang
{"title":"System design considerations of highly-integrated UHF RFID reader transceiver RF front-end","authors":"Jingchao Wang, B. Chi, Xuguang Sun, Tongqiang Gao, Chun Zhang, Zhihua Wang","doi":"10.1109/ICSICT.2008.4734855","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734855","url":null,"abstract":"Nowadays the implementation of highly integrated UHF RFID reader transceiver RF front-ends with excellent performance is demanding and is still challenging. This paper presents a number of design considerations from the system point of view, including the choice of receiver/transmitter front-end architecture, isolation between transmitter and receiver, power efficiency of the transmitter. Some critical system performance issues like sensitivity, noise figure, dynamic range and AGC operation, LO phase noise, et al. are also presented.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134019130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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