IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.最新文献_第9页

Speedups from partitioning software kernels to FPGA hardware in embedded SoCs 在嵌入式soc中，从划分软件内核到FPGA硬件的加速

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579917

M. D. Galanis, G. Dimitroulakos, A. Kakarountas, C. Goutis

{"title":"Speedups from partitioning software kernels to FPGA hardware in embedded SoCs","authors":"M. D. Galanis, G. Dimitroulakos, A. Kakarountas, C. Goutis","doi":"10.1109/SIPS.2005.1579917","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579917","url":null,"abstract":"This paper presents a hardware/software partitioning methodology for improving performance in single-chip systems comprised by processor and reconfigurable logic. The reconfigurable logic is realized by field programmable gate array technology. Critical software parts are selected for acceleration on the reconfigurable logic. A generic hybrid system-on-chip platform, which can model the majority of existing processor-FPGA systems, is considered by the method. The partitioning method uses an automated kernel identification process at the basic-block level for detecting critical software portions. Three different instances of the generic platform and two sets of benchmarks are used in the experiments. The analysis on five real-life applications showed that these applications spend an average of 69% of their instruction count in 11% on average of their code. The extensive experimentation illustrates that for the systems composed by 32-bit processors the speedup of five applications ranges from 1.3 to 3.7 relative to an all software solution. For a platform composed by an 8-bit processor, the performance gains of eight DSP algorithms are considerably greater, since the average speedup equals 28.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115997218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

On the way to an H.264 HW/SW reference model: a SystemC modeling strategy to integrate selected IP-blocks with the H.264 software reference model 在通往H.264硬件/软件参考模型的道路上:将选定的ip块与H.264软件参考模型集成在一起的SystemC建模策略

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579860

I. Amer, M. Sayed, Wael Badawy, G. Jullien

引用次数: 9

A Navier-Stokes processor for biomedical applications 生物医学应用的纳维-斯托克斯处理器

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579895

V. Zygouris, K. Karagianni, T. Stouraitis

引用次数: 3

Image quality assessment metrics based on multi-scale edge presentation 基于多尺度边缘表示的图像质量评价方法

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579888

Guangtao Zhai, Wenjun Zhang, Xiaokang Yang, Yi Xu

{"title":"Image quality assessment metrics based on multi-scale edge presentation","authors":"Guangtao Zhai, Wenjun Zhang, Xiaokang Yang, Yi Xu","doi":"10.1109/SIPS.2005.1579888","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579888","url":null,"abstract":"We propose two image quality assessment metrics named multi-scale modular similarity (M/sup 2/S) and multi-scale modular maxima similarity (M/sup 3/S). It has been well known 1) multi-scale analysis is an effective decomposition technique in image processing, and 2) contours and edges analyses are crucial in the understanding of natural scenes. Motivated by these two facts, we attempt to develop quality assessment metrics using multi-scale edges presentation. We decompose an image with un-decimated dyadic wavelet transform, and then develop M/sup 2/S metric to evaluate the quality of images by comparing the modulus across scales of wavelet transform. Multi-scale edges are defined as local maxima of modulus, which often contain the most important information of the image. As a further step of M/sup 2/S metric, M/sup 3/S only uses the multi-scale edge information. M/sup 3/S is therefore essentially a reduced-reference image quality metric. Extensive experiments indicate that in most cases, the prediction abilities of these two proposed metrics are similarly excellent and both outperform the widely used PSNR and the simple structural similarity metrics.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128579943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 48

From NoC security analysis to design solutions 从NoC安全分析到设计解决方案

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579858

S. Evain, J. Diguet

引用次数: 66

Low power techniques for MP3 audio decoder using subband cut-off approach 采用子带截止方法的MP3音频解码器低功耗技术

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579877

T. Tsai, Chun-Kai Wang, Chun-Nan Liu

引用次数: 1

Diagonal low-density parity-check code for simplified routing in decoder 用于简化解码器路由的对角低密度奇偶校验码

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579966

E. Kim, G. Choi

引用次数: 9

SIMD implementation of interpolation in algebraic soft-decision Reed-Solomon decoding SIMD实现插值中的代数软判决里德-所罗门解码

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579965

L. Boulianne, W. Gross

引用次数: 2

Efficient motion vector refinement architecture for sub-pixel motion estimation systems 亚像素运动估计系统的高效运动矢量细化结构

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579885

T. Dias, N. Roma, L. Sousa

引用次数: 8

Parallel implementations with low-complexity of rotation-based adaptive filters 基于旋转自适应滤波器的低复杂度并行实现

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579936

M. Bhouri

引用次数: 1