IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.最新文献_第5页

Optimizing data intensive window-based image processing on reconfigurable hardware boards 在可重构硬件板上优化基于窗口的数据密集型图像处理

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579918

Haiqian Yu, M. Leeser

引用次数: 10

Cross-layer energy-throughput evaluation of multi-hop/path communication and link adaptation for IEEE 802.11a IEEE 802.11a多跳/路径通信和链路自适应的跨层能量吞吐量评估

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579832

S. Pollin, R. Goyens, W. Cleeren, B. Bougard

{"title":"Cross-layer energy-throughput evaluation of multi-hop/path communication and link adaptation for IEEE 802.11a","authors":"S. Pollin, R. Goyens, W. Cleeren, B. Bougard","doi":"10.1109/SIPS.2005.1579832","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579832","url":null,"abstract":"Future wireless communication devices are expected to support a wide range of applications, while coping with stringent energy budget requirements. Delivering at each moment in time the required performance with minimal energy consumption is a promising energy management technique to enable pervasive wireless networking. Considering transmission energy only, the use of multiple small hops results in a decrease of the energy consumption. On the other hand, decreasing the transmission rate of a single hop similarly results in a decrease of the energy needed to deliver a bit. In this paper we compare the use of multiple small hops along different paths with a single large hop in the energy-throughput design space. In contrast with earlier work, realistic transceiver models are used, that cover the complete MAC, transmit and receive chain and support different transmission rates. Results show that, compared to single hop link adaptation, the use of multiple hops in indoor environments is only optimal in the energy-throughput space for distances larger than 30 m or when there are obstacles present that can be avoided in alternative paths. For those larger distances, significant gains are possible though. Hence, to achieve energy optimal operation in 802.11a networks, it is important to adapt jointly the physical layer constellation and network layer path selection.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127706353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

The generalized quadrature modulation structures 广义正交调制结构

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579922

Jie-Cherng Liu

引用次数: 0

Image transmission in sensor networks 传感器网络中的图像传输

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579960

K. Lui, E. Lam

引用次数: 11

A multiprocessor based packet-switch: performance analysis of the communication infrastructure 基于多处理器的分组交换:通信基础设施的性能分析

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579859

S. Tota, M. Casu, M. Roch, M. Zamboni

{"title":"A multiprocessor based packet-switch: performance analysis of the communication infrastructure","authors":"S. Tota, M. Casu, M. Roch, M. Zamboni","doi":"10.1109/SIPS.2005.1579859","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579859","url":null,"abstract":"The intra-chip communication infrastructures are receiving always more attention since they are becoming a crucial part in the development of current SoCs. Due to the high availability of pre-characterized hard-IP, the complexity of the design is moving toward global interconnections which are introducing always more constraints at each technology node. Power consumption, timing closure, bandwidth requirements, time to market, are some of the factors that are leading to the proposal of new solutions for next generation multi-million SoCs. The need of high programmable systems and the high gate-count availability is moving always more attention on multiprocessors systems (MP-SoC) and so an adequate solution must be found for the communication infrastructure. One of the most promising technologies is the network-on-chip (NoC) architecture, which seems to better fit with the new demanding complexity of such systems. Before starting to develop new solutions, it is crucial to fully understand if and when current bus architectures introduce strong limitations in the development of high speed systems. This article describes a case study of a multiprocessor based ethernet packet-switch application with a shared-bus communication infrastructure. This system aims to depict all the bottlenecks which a shared-bus introduces under heavy load. What emerges from this analysis is that, as expected, a shared-bus is not scalable and it strongly limits whole system performances. These results strengthen the hypothesis that new communication architectures (like the NoC) must be found.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115077569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Flexible hardware architecture for 2-D separable scaling using convolution interpolation 利用卷积插值实现二维可分缩放的灵活硬件结构

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579953

J. Arnabat-Benedicto, F.C. Tormo

引用次数: 0

Classification of fetal heart rate using grammatical evolution 胎儿心率的语法演化分类

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579906

D. Gavrilis, I. Tsoulos

引用次数: 9

Signature verification based on line directionality 基于线路方向的签名验证

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579890

E. Zois, A. Nassiopoulos, V. Anastassopoulos

引用次数: 6

Low-power MPEG-4 video encoder design 低功耗MPEG-4视频编码器设计

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579880

K. Denolf, A. Chirila-Rus, D. Verkest

引用次数: 7

The high throughput and low memory access design of sub-pixel interpolation for H.264/AVC HDTV decoder H.264/AVC高清电视解码器中亚像素插值的高吞吐量和低内存访问设计

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579882

Mo Li, Ronggang Wang, Wuchen Wu

引用次数: 9