2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)最新文献_第4页

NoC-sprinting: Interconnect for fine-grained sprinting in the dark silicon era noc -sprint:暗硅时代细粒度冲刺的互连

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593165

J. Zhan, Yuan Xie, Guangyu Sun

{"title":"NoC-sprinting: Interconnect for fine-grained sprinting in the dark silicon era","authors":"J. Zhan, Yuan Xie, Guangyu Sun","doi":"10.1145/2593069.2593165","DOIUrl":"https://doi.org/10.1145/2593069.2593165","url":null,"abstract":"The rise of utilization wall limits the number of transistors that can be powered on in a single chip and results in a large region of dark silicon. While such phenomenon has led to disruptive innovation in computation, little work has been done for the Network-on-Chip (NoC) design. NoC not only directly influences the overall multi-core performance, but also consumes a significant portion of the total chip power. In this paper, we first reveal challenges and opportunities of designing power-efficient NoC in the dark silicon era. Then we propose NoC-Sprinting: based on the workload characteristics, it explores fine-grained sprinting that allows a chip to flexibly activate dark cores for instantaneous throughput improvement. In addition, it investigates topological/routing support and thermal-aware floorplanning for the sprinting process. Moreover, it builds an efficient network power-management scheme that can mitigate the dark silicon problems. Experiments on performance, power, and thermal analysis show that NoC-sprinting can provide tremendous speedup, increase sprinting duration, and meanwhile reduce the chip power significantly.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126187041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

Reduction operator for wide-SIMDs reconsidered 重新考虑了宽simd的缩减算子

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593198

Luc Waeijen, Dongrui She, H. Corporaal, Yifan He

{"title":"Reduction operator for wide-SIMDs reconsidered","authors":"Luc Waeijen, Dongrui She, H. Corporaal, Yifan He","doi":"10.1145/2593069.2593198","DOIUrl":"https://doi.org/10.1145/2593069.2593198","url":null,"abstract":"It has been shown that wide Single Instruction Multiple Data architectures (wide-SIMDs) can achieve high energy efficiency, especially in domains such as image and vision processing. In these and various other application domains, reduction is a frequently encountered operation, where multiple input elements need to be combined into a single element by an associative operation, e.g. addition or multiplication. There are many applications that require reduction such as: partial histogram merging, matrix multiplication and min/max-finding. Wide-SIMDs contain a large number of processing elements (PEs), which in general are connected by a minimal form of interconnect for scalability reasons. To efficiently support reduction operations on wide-SIMDs with such a minimal interconnect, we introduce two novel reduction algorithms which do not rely on complex communication networks or any dedicated hardware. The proposed approaches are compared with both dedicated hardware and other software solutions in terms of performance, area, and energy consumption. A practical case study demonstrates that the proposed software approach has much better generality, flexibility and no additional hardware cost. Compared to a dedicated hardware adder tree, the proposed software approach saves 6.8% area with a performance penalty of only 6.5%.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128547974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Retention trimming for wear reduction of flash memory storage systems 用于减少快闪记忆体储存系统磨损的保留修整

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593203

Liang Shi, Kaijie Wu, Mengying Zhao, C. Xue, E. Sha

引用次数: 16

An efficient bi-criteria flow channel routing algorithm for flow-based microfluidic biochips 基于流动的微流控生物芯片的高效双准则流道路由算法

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593084

Chun-Xun Lin, Chih-Hung Liu, I-Che Chen, D. T. Lee, Tsung-Yi Ho

{"title":"An efficient bi-criteria flow channel routing algorithm for flow-based microfluidic biochips","authors":"Chun-Xun Lin, Chih-Hung Liu, I-Che Chen, D. T. Lee, Tsung-Yi Ho","doi":"10.1145/2593069.2593084","DOIUrl":"https://doi.org/10.1145/2593069.2593084","url":null,"abstract":"Rapid growth in capacity makes flow-based microfluidic biochips a promising candidate for biochemical analysis because they can integrate more complex functions. However, as the number of components grows, the total length of flow channels between components must increase exponentially. Recent empirical studies show that long flow channels are vulnerable due to blocking and leakage defects. Thus, it is desirable to minimize the total length of flow channels for robustness. Also, for timing-sensitive biochemical assays, increase in the longest length of flow channel will delay the assay completion time and lead to variation of fluid, thereby affecting the correctness of outcome. The increasing number of components, including the pre-placed components, on the chip makes the flow channel routing problem even more complicated. In this paper, we propose an efficient obstacle-avoiding rectilinear Steiner minimum tree algorithm to deal with flow channel routing problem in flow-based microfluidic biochips. Based on the concept of Kruskal algorithm and formulating the considerations as a bi-criteria function, our algorithm is capable of simultaneously minimizing the total length and the longest length of flow channel.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132205858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44

Selective inversion of inductance matrix for large-scale sparse RLC simulation 大规模稀疏RLC仿真中电感矩阵的选择性反演

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593213

Ifigeneia Apostolopoulou, Konstantis Daloukas, N. Evmorfopoulos, G. Stamoulis

引用次数: 5

An automobile detection algorithm development for automated emergency braking system 汽车自动紧急制动系统检测算法的开发

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593083

L. Xia, Tran Duc Chung, K. A. A. Kassim

引用次数: 9

Time-analysable non-partitioned shared caches for real-time multicore systems 用于实时多核系统的可时间分析的非分区共享缓存

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593235

Mladen Slijepcevic, Leonidas Kosmidis, J. Abella, E. Quiñones, F. Cazorla

引用次数: 34

FIGHT-metric: Functional identification of gate-level hardware trustworthiness 战斗度量:门级硬件可信度的功能识别

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2596681

Dean Sullivan, J. Biggers, Guidong Zhu, Shaojie Zhang, Yier Jin

引用次数: 31

High-level synthesis for run-time hardware Trojan detection and recovery 运行时硬件木马检测和恢复的高级综合

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593150

Xiaotong Cui, K. Ma, Liang Shi, Kaijie Wu

引用次数: 49

Multi-objective local-search optimization using reliability importance measuring 基于可靠性重要性度量的多目标局部搜索优化

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593164

Faramarz Khosravi, Felix Reimann, M. Glaß, J. Teich

{"title":"Multi-objective local-search optimization using reliability importance measuring","authors":"Faramarz Khosravi, Felix Reimann, M. Glaß, J. Teich","doi":"10.1145/2593069.2593164","DOIUrl":"https://doi.org/10.1145/2593069.2593164","url":null,"abstract":"In recent years, reliability has become a major issue and objective during the design of embedded systems. Here, different techniques to increase reliability like hardware-/software-based redundancy or component hardening are applied systematically during Design Space Exploration (DSE), aiming at achieving highest reliability at lowest possible cost. Existing approaches typically solely provide reliability measures, e. g. failure rate or Mean-Time-To-Failure (MTTF), to the optimization engine, poorly guiding the search which parts of the implementation to change. As a remedy, this work proposes an efficient approach that (a) determines the importance of resources with respect to the system's reliability and (b) employs this knowledge as part of a local search to guide the optimization engine which components/design decisions to investigate. First, we propose a novel approach to derive Importance Measures (IMs) using a structural evaluation of Success Trees (STs). Since ST-based reliability analysis is already used for MTTF calculation, our approach comes at almost no overhead. Second, we enrich the global DSE with a local search. Here, we propose strategies guided by the IMs that directly change and enhance the implemen- tation. In our experimental setup, the available measures to enhance reliability are the selection of hardening levels during resource allocation and software-based redundancy during task binding; exemplarily, the proposed local search considers the selected hardening levels. The results show that the proposed method outperforms a state-of-the-art approach regarding optimization quality, particularly in the search for highly-reliable yet affordable implementations - at negligible runtime overhead.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125279607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14