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A compact modeling of drain current in PD/FD SOI MOSFETs PD/FD SOI mosfet漏极电流的紧凑建模
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161500
M. Maddah, S. Bolouki, A. Afzali-Kusha, M. Nokali
{"title":"A compact modeling of drain current in PD/FD SOI MOSFETs","authors":"M. Maddah, S. Bolouki, A. Afzali-Kusha, M. Nokali","doi":"10.1109/ICM-02.2002.1161500","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161500","url":null,"abstract":"In this paper, a unified analytical I-V model for silicon-on-insulator (SOI) MOSFET is presented. The model is valid for possible transitions between partially-depleted (PD) and fully-depleted (FD) modes during the transistor operation. It is based on a non-pinned surface potential approach that is valid for all regions of operation. The surface potential is calculated accurately and efficiently in this model where small geometry effects such as channel length modulation (CLM) and high field mobility effects are also included. It also considers the self-heating effect, which is important for complete modeling of SOI devices. For including the floating body effect, the parasitic currents in each mode of operation is modeled with a proper formulation while a smoothing function is invoked for the transition between the operation modes. A comparison between the model and the experimental results shows good agreement over a wide range of drain and gate voltages.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115007867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The synchronous oscillator in frequency generation: an overview 频率产生中的同步振荡器:概述
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161517
Y. Deval, J. Bégueret, H. Lapuyade, P. Fouillat, E. Kerhervé
{"title":"The synchronous oscillator in frequency generation: an overview","authors":"Y. Deval, J. Bégueret, H. Lapuyade, P. Fouillat, E. Kerhervé","doi":"10.1109/ICM-02.2002.1161517","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161517","url":null,"abstract":"The Synchronous Oscillator (SO) as a frequency generation device is presented, and the impact of the technology on the circuit behavior is discussed. Several prototypes, either in bipolar, CMOS or SiGe BiCMOS technologies are presented and discussed.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115146317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Comparison of constant coefficient multipliers for CSD and Booth recoding 常系数乘法器在CSD和Booth编码中的比较
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161498
A. Hu, A. Al-Khalili
{"title":"Comparison of constant coefficient multipliers for CSD and Booth recoding","authors":"A. Hu, A. Al-Khalili","doi":"10.1109/ICM-02.2002.1161498","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161498","url":null,"abstract":"In this paper, the designs of constant coefficient multipliers (KCM) with canonical signed-digit (CSD) and Booth recoding are presented and compared. It is shown that the designs with CSD recoding have fewer additions than those with Booth recoding. But in some cases, with pre-calculated partial products, the number of additions in the latter designs can be reduced significantly. Pre-calculation can also be used in CSD KCM design. ASIC designers should make the choice according to the constant multiplier.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134334571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 1.5-V supply, 10.7-MHz, bandpass g/sub m/-C filter in a 0.6/spl mu/m standard CMOS technology 1.5 v电源，10.7 mhz，带通g/sub / c滤波器，采用0.6/spl mu/m标准CMOS技术
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161493
A. Tajalli, M. Atarodi
{"title":"A 1.5-V supply, 10.7-MHz, bandpass g/sub m/-C filter in a 0.6/spl mu/m standard CMOS technology","authors":"A. Tajalli, M. Atarodi","doi":"10.1109/ICM-02.2002.1161493","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161493","url":null,"abstract":"A 1.5-V single supply, second order continuous-time bandpass filter, on a 0.6/spl mu/m standard CMOS process is designed. The THD of the transconductor for a 0.7V/sub pp/ input, is -50dB at 10-MHz. In the proposed transconductor structure, the whole circuit, apart from a dc level-shifter based on a voltage doubler, is biased by a single 1.5-V supply. Due to this structure, a high current voltage doubler is not required and the whole filter draws less than 70/spl mu/m current from this doubler making an on-chip voltage doubler feasible. Also, a new linear common-mode detector with high-frequency response is designed to stabilize the output common-mode voltage.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"46 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132433735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of drain current characteristics of SOI MOSFETs using neural networks 基于神经网络的SOI mosfet漏极电流特性建模
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161509
S. Hatami, M. Azizi, H. Bahrami, D. Motavalizadeh, A. Afzali-Kusha
{"title":"Modeling of drain current characteristics of SOI MOSFETs using neural networks","authors":"S. Hatami, M. Azizi, H. Bahrami, D. Motavalizadeh, A. Afzali-Kusha","doi":"10.1109/ICM-02.2002.1161509","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161509","url":null,"abstract":"This paper presents neural network approaches for modeling the I-V characteristics of Silion-on-Insulator (SOI) MOSFETs. The modeling approach is fast and accurate making it suitable for circuit simulators. In our modeling, two different neural network architectures, MultiLayer Perceptron (MLP) and Generalized Radial Basis Function (GRBF), are used and compared. To increase the training efficiency of the neural network, a modular method has been utilized. The drain current characteristic obtained by the neural network model is compared to simulation data. The comparison shows excellent agreements with relative errors of less than 1.1% over a wide range of drain and gate voltages and channel lengths.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124425493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new Josephson /spl delta/-gate ternary-valued logic 一种新的Josephson /spl δ /门三值逻辑
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161541
A. Haidar, Z. Othman, M. Morisue
{"title":"A new Josephson /spl delta/-gate ternary-valued logic","authors":"A. Haidar, Z. Othman, M. Morisue","doi":"10.1109/ICM-02.2002.1161541","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161541","url":null,"abstract":"A new Josephson circuit of multi-valued logic gate (Josephson ternary /spl delta/-gate) is proposed. The simulation result of the Josephson /spl delta/-gate circuit demonstrated the feasibility and the reliability operations, where very low power consumption, and ultra high speed switching operation have been achieved. Mathematical properties of /spl delta/-gate are introduced. The /spl delta/-gate forms a complete set (completeness) with the ternary constant set {-1, 0. 1}. Based on /spl delta/-gate, it is possible to analyze, synthesize and realize an arbitrary ternary logic function of n-input variables. An application, a ternary logic half-adder is presented, its simulation results shows reliable operation and excellent performance. Finally, the /spl delta/-gate can transfer signals from gate to gate without loss of amplitude, the /spl delta/-gate is a multiplexor and it is very effective for a MV-FPGA (multi-valued field-programmable gate arrays) building blocks.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"1077 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120878735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An optimized methodology to design CMOS operational amplifier CMOS运算放大器的优化设计方法
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161486
M. Loulou, S. Ait Ali, M. Fakhfakh, N. Masmoudi
{"title":"An optimized methodology to design CMOS operational amplifier","authors":"M. Loulou, S. Ait Ali, M. Fakhfakh, N. Masmoudi","doi":"10.1109/ICM-02.2002.1161486","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161486","url":null,"abstract":"In this paper we present a method to optimize the design of CMOS operational amplifier. The purpose of this work is to give an optimal transistor sizing methodology in order to reach the op-amp desired characteristics. This is achieved by mean of simple calculations and accessible mathematic software. The idea consists of a mathematical formulation based on level 1 SPICE MOS model. Then, an objective function is defined according to the performances required. By mean of Maple software, we determine the optimal op-amp parameters. The proposed method is presented and applied to the design of standard CMOS op-amp using CMOS 0.35/spl mu/m process. Simulations using PSPICE are presented and compared to theoretical calculations show the efficiency of our method.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115482166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Adaptive wire adjustment for bounded skew clock distribution network using quadratic tree 基于二次树的有界斜时钟配电网自适应导线调整
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161487
H. Saaied, D. Al-Khalili, A. Al-Khalili, M. Nekili
{"title":"Adaptive wire adjustment for bounded skew clock distribution network using quadratic tree","authors":"H. Saaied, D. Al-Khalili, A. Al-Khalili, M. Nekili","doi":"10.1109/ICM-02.2002.1161487","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161487","url":null,"abstract":"Recently, a new approach, called Adaptive Wire Adjustment (AWA), was proposed for the synthesis of Clock Distribution Networks (CDNs) in order to cope with modifications required in the design process. The main drawback of the AWA is its slow convergence. In this paper, we propose to use a quadratic tree instead of a binary tree in order to speed up the AWA's convergence. The proposed approach reduces the skew iteratively by selecting a balancing node (BN), selecting the topology of connecting the BN to its children, and adjusting the edges so that the skew gets smaller, In addition to the faster convergence, the quadratic tree structure offers a topology flexibility that helps to reduce the wire length further. The procedure of selecting the connection topology and determining the edge adjustments are based on the Elmore delay model. The performance of the proposed algorithm is investigated using different random sets of registers. The results show that the number of iterations can be reduced effectively as the number of clock pins increases. Further, for CDNs of 1024, 4096 and 16384 clock pins, the proposed technique can reduce the CDNs total wire length by 4.9%, 14.7% and 27.6% respectively.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129946326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Maximum of mutual inductance by inductive link 感应环节互感的最大值
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161544
M. Chaoui, H. Ghariani, M. Lahiani, F. Sellami
{"title":"Maximum of mutual inductance by inductive link","authors":"M. Chaoui, H. Ghariani, M. Lahiani, F. Sellami","doi":"10.1109/ICM-02.2002.1161544","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161544","url":null,"abstract":"This paper presents inductive link between various coils or various forms to protect the reserve of unidirectional energy and from bi-directional data in the implantables electronic devices. Study will rest on the increase of the efficiency allocated by the tolerance to the lateral, longitudinal and even angular displacement between the external coil (transmitter) and the implanted coil (receiver).","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"12 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116672399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 1.8V high dynamic range CMOS Gm-c filter for portable video systems 用于便携式视频系统的1.8V高动态范围CMOS Gm-c滤波器
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161491
S. Mehrmanesh, H.A. Aslanzadeh, M.B. Vahidfar, M. Atarodi
{"title":"A 1.8V high dynamic range CMOS Gm-c filter for portable video systems","authors":"S. Mehrmanesh, H.A. Aslanzadeh, M.B. Vahidfar, M. Atarodi","doi":"10.1109/ICM-02.2002.1161491","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161491","url":null,"abstract":"A 4th order, 5 MHz, lowpass Butterworth Gm-c filter has been combined with a low noise low-voltage amplifier to form a lowpass filter for video applications. In this filter an improved transconductor and a powerful method is used to adjust the transconductance gain for tuning application. A continuous variable gain current-to-current converter is used to tune the transconductor value. The THD of the filter is -77 dB for 1 V/sub ppd/ input signal. Input referred noise is 40 nV//spl radic/Hz in the worst case. All the circuits are designed based on a 0.25 /spl mu/m CMOS process technology with a single 1.8 V supply.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117100288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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