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Controlling on-chip inductive coupling of signal busses through swizzling 通过搅拌控制片上信号总线的电感耦合
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161525
B. Soudan
{"title":"Controlling on-chip inductive coupling of signal busses through swizzling","authors":"B. Soudan","doi":"10.1109/ICM-02.2002.1161525","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161525","url":null,"abstract":"On-chip inductive coupling effects have been shown to depend directly on the overlap length between adjacent signal wires. This has major effect on global signal busses in high performance microprocessors. These busses are usually routed as a bundle containing a large number of signals traveling for long distances. In this paper, we propose a routing technique known as swizzling to control the inductive coupling effects between signal wires in global signal busses. The advantage of this technique is reducing the inductive coupling effects with zero area or routing resource cost.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125006252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
FPGA implementation of a UMTS turbo coder/decoder 一个UMTS turbo编码器/解码器的FPGA实现
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161529
C. Francis, J. Farah, M. Chendeb, F. Kassem
{"title":"FPGA implementation of a UMTS turbo coder/decoder","authors":"C. Francis, J. Farah, M. Chendeb, F. Kassem","doi":"10.1109/ICM-02.2002.1161529","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161529","url":null,"abstract":"The aim of this paper is to implement a Third Generation Mobile Communication turbo-coder and a turbo-decoder in an FPGA circuit in order to evaluate the architecture complexity of both devices. The implemented devices are to be coupled to a Digital Signal Processor in charge of all signal processing base-band operations in a third generation mobile terminal.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131511984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An interleaving based algorithm for ordering variables in shared BDDS 基于交错的共享BDDS变量排序算法
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161542
E. Shaaban, A. Salem, A. Moniem Wahdan
{"title":"An interleaving based algorithm for ordering variables in shared BDDS","authors":"E. Shaaban, A. Salem, A. Moniem Wahdan","doi":"10.1109/ICM-02.2002.1161542","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161542","url":null,"abstract":"In this paper, a new algorithm for finding a good initial order for the multiple output combinational circuits is proposed. The algorithm uses the dynamic weight assignment method combined with the interleaving technique. The proposed algorithm computed one good order for all outputs in the same time. The efficiency of the proposed technique is shown on the ISCAS-85 benchmarks.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"106 33","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131913574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low power, low voltage, 10bit-50MSPS pipeline ADC dedicated for front-end ultrasonic receivers 低功耗，低电压，10bit-50MSPS流水线ADC专用于前端超声接收机
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161534
K. El-Sankary, A. Kassem, R. Chebli, M. Sawan
{"title":"Low power, low voltage, 10bit-50MSPS pipeline ADC dedicated for front-end ultrasonic receivers","authors":"K. El-Sankary, A. Kassem, R. Chebli, M. Sawan","doi":"10.1109/ICM-02.2002.1161534","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161534","url":null,"abstract":"This paper concerns the design and the implementation of a low power, low voltage 10bit-50MS/s pipeline analog to digital converter (ADC) dedicated to ultrasonic receivers. The ADC is used in the front-end stage to convert the signals coming from the time gain compensator (TGC) of the handheld ultrasonic apparatus. The proposed architecture is based on 1.5 bits per stage pipeline structure followed by a digital offset compensation to relax the constraints on the analog circuitry. The converter is implemented in digital CMOS 0.18 /spl mu/m technology, the circuit occupies an active area of 1.2 mm/sup 2/, the input differential voltage dynamic range is chosen to be 1.6 Vpp and the power consumption is found to be 31 mW from 1.8 V supply.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122018175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
FPGA-based load balancer for Internet servers 基于fpga的Internet服务器负载平衡器
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161527
L. Harik, A. Kayssi
{"title":"FPGA-based load balancer for Internet servers","authors":"L. Harik, A. Kayssi","doi":"10.1109/ICM-02.2002.1161527","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161527","url":null,"abstract":"Server load balancing refers to the concept of having multiple parallel servers offering the same service to clients on the Internet, in order to enhance the reliability and performance of the service. To coordinate the operation of the multiple servers, a load balancer is needed. We have implemented a Network Address Translation (NAT) Load Balancer in hardware using a Field-Programmable Gate Array (FPGA). The preliminary results show that the NAT Load Balancer on the FPGA is able to handle gigabit per second speeds.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115264972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Elementary amplitude and distortion evaluation in Wien and phase shift oscillators 维恩和相移振荡器的基本幅度和失真评估
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161515
R. Malhamé
{"title":"Elementary amplitude and distortion evaluation in Wien and phase shift oscillators","authors":"R. Malhamé","doi":"10.1109/ICM-02.2002.1161515","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161515","url":null,"abstract":"Oscillator theory is typically introduced to undergraduate electrical engineers using a quasilinear analysis based on transfer functions for what is, by essence, a nonlinear phenomenon. For negative resistance oscillators, a more rigorous treatment based on differential equations is presented in L.O. Chua et al. (1987), and while it sheds a significant amount of light on the nonlinear dynamics involved, it fails to give an elementary treatment of what is after all the essential difficulty in low distortion sinusoidal oscillator theory: amplitude and distortion evaluation. In this work, under an assumption of low distortion, we compute an asymptotic approximation of the amplitude of oscillation based on an elementary analysis of the evolution of the total energy stored in energy storing circuit elements over a cycle, for both Wien and phase shift oscillators. Interestingly, we show that amplitudes in both oscillators are characterized by very similar transcendental equations involving appropriately defined normalized variables. Also, the procedure herein proposed appears to be generalizable to arbitrary types of low distortion sinusoidal oscillators.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125146415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fast parallel architecture for syndrome convolutional decoder 综合征卷积解码器的快速并行结构
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161489
A. M'sir, A. Dandache, F. Monteiro, B. Lepley
{"title":"Fast parallel architecture for syndrome convolutional decoder","authors":"A. M'sir, A. Dandache, F. Monteiro, B. Lepley","doi":"10.1109/ICM-02.2002.1161489","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161489","url":null,"abstract":"This paper presents a parallel architecture for the syndrome convolutional decoder. It is build-up of a parallel convolutional encoder and a syndrome correction block. The proposed architecture combines combinatorial and pipeline parallelism techniques. Using both techniques allows to limit the critical path increase on higher levels of parallelism, i.e. limit the operating frequency decrease. Data rates up to 4.78 Gbits/s have been obtained for a 1/2 -rate code implementation on a FPGA device of the ALTERA Flex10KE family.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"1154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128199174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1.5V multigigahertz CMOS tunable image reject notch filter 一种1.5V多兆赫CMOS可调谐图像抑制陷波滤波器
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161516
R. A. Baki, N. El-Gamal
{"title":"A 1.5V multigigahertz CMOS tunable image reject notch filter","authors":"R. A. Baki, N. El-Gamal","doi":"10.1109/ICM-02.2002.1161516","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161516","url":null,"abstract":"This paper presents a new RF notch filter topology for image rejection in heterodyne receivers. The circuit is combined with a cascode low noise amplifier (LNA) and an output buffer for testing purposes. It is implemented with standard CMOS 0.18/spl mu/m technology. The notch filter is tunable from 10.5 to 11.1GHz. Up to 10dB controllable gain is obtained from the LNA in the pass band at 6.5GHz. A -50dB image rejection is realized by using on chip inductor Q-factor enhancement techniques. At the maximum in band gain of 12dB and -50dB image rejection, the circuit consumes 22mW of power with a noise figure of 2.4dB, a -12.5dB IIP3, from a 1.5V power supply.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130947260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Experimental study of total ionizing dose radiation effects on MOS capacitor 总电离剂量辐射对MOS电容影响的实验研究
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161546
Karam Sharashar, S. Kayed
{"title":"Experimental study of total ionizing dose radiation effects on MOS capacitor","authors":"Karam Sharashar, S. Kayed","doi":"10.1109/ICM-02.2002.1161546","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161546","url":null,"abstract":"The aim of this paper is to investigate the total ionizing dose (TID) radiation effects on MOS capacitor wafer samples that are locally fabricated for this purpose. The oxide was prepared by dry-wet-dry oxidation technique at 1000 /spl deg/C using N-type Si substrate of about 3 /spl Omega/.cm. The samples have been exposed to irradiation at different doses from 1Krad(SiO/sub 2/) up to 1Mrad(SiO/sub 2/) using two different Gamma sources for high and low radiation rates, a shift in C-V curves as a flat-band shifted from 0.3 up to 2.5V and interface states of irradiated samples increased from 2.45*10/sup 12/ up to 250*10/sup 12/ eV/sup -1/ cm/sup -2/. Shelf annealing effects have also been investigated.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127825773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fingerprint recognition using fuzzy artmap neural network architecture 指纹识别采用模糊艺术图神经网络架构
The 14th International Conference on Microelectronics, Pub Date : 2002-12-11 DOI: 10.1109/ICM-02.2002.1161519
I. Dagher, Wael Helwe, Firass Yassine
{"title":"Fingerprint recognition using fuzzy artmap neural network architecture","authors":"I. Dagher, Wael Helwe, Firass Yassine","doi":"10.1109/ICM-02.2002.1161519","DOIUrl":"https://doi.org/10.1109/ICM-02.2002.1161519","url":null,"abstract":"In this paper, a neural network architecture, Fuzzy Artmap (FAM), was used to classify fingerprints. A fingerprint database of the University of Balamand (UOB) was created. The algorithm uses the filterbank representation which captures the local and global details in a fingerprint as a 320-byte fixed length FingerCode which is suitable for storage. In the first stage, the fingerprint is classified using FAM to one of the five categories (whorl, left loop, right loop, arch, and tented arch). Then, the algorithm matches the fingerprint by searching in the specific category in the database. Matching is done using the two corresponding FingerCodes and thus, is very fast.","PeriodicalId":433175,"journal":{"name":"The 14th International Conference on Microelectronics,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114207313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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