2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia最新文献

Sequential specification of time-aware stream processing applications (Extended abstract) 时间感知流处理应用程序的顺序规范(扩展摘要)

2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia Pub Date : 2012-10-11 DOI: 10.1145/2435227.2435231

Stefan J. Geuns, J. Hausmans, M. Bekooij

引用次数: 8

Support for power efficient mobile video playback on simultaneous hybrid display 支持同时混合显示的节能移动视频播放

2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia Pub Date : 2012-10-01 DOI: 10.1109/ESTIMedia.2012.6507035

Y. Wen, Ziyi Liu, W. Shi, Yifei Jiang, A. Cheng, Feng Yang, Abhinav Kohar

{"title":"Support for power efficient mobile video playback on simultaneous hybrid display","authors":"Y. Wen, Ziyi Liu, W. Shi, Yifei Jiang, A. Cheng, Feng Yang, Abhinav Kohar","doi":"10.1109/ESTIMedia.2012.6507035","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2012.6507035","url":null,"abstract":"Mobile devices, such as smartphones, e-books, and tablets, have limited battery capability because of the constraint of battery size and mobility requirement. However the large color displays on those devices put more tensions on this situation as the displays consume a large portion of the total battery power. A TOLED-EPD hybrid display that integrates a transparent OLED (TOLED) with an electrophoretic display (EPD) has been emerging to reduce the energy usage of displays. The technology displays information selectively on one of the displays based on the update rate of content, thus reduces the energy usage. In this paper, we propose a design of mobile video playback, Decoder4Hybrid, for the hybrid displays. The proposed approach supports encoded video playback based on the update frequency of each block, which is exploited by the hybrid display controller to determine which display should be used to show a MPEG encoded block. A fast DCT-based heuristic algorithm is proposed to detect the changes between frames at block level with minimal computation cost. Experimental results show that the proposed approach can save up to 40% power with acceptable video quality.","PeriodicalId":431615,"journal":{"name":"2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131498569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A lifetime aware buffer assignment method for streaming applications on DRAM/PRAM hybrid memory (Extended abstract) 基于DRAM/PRAM混合存储器的流应用缓冲区分配方法(扩展摘要)

2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia Pub Date : 2012-10-01 DOI: 10.1145/2435227.2435232

Daeyoung Lee, Hyunok Oh

引用次数: 7

AVid: Annotation driven video decoding for hybrid memories AVid:用于混合存储器的注释驱动视频解码

2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia Pub Date : 2012-10-01 DOI: 10.1109/ESTIMedia.2012.6507022

Liviu Codrut Stancu, L. A. Bathen, N. Dutt, A. Nicolau

引用次数: 11

Multi-objective mapping optimization via problem decomposition for many-core systems 基于问题分解的多核系统多目标映射优化

2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia Pub Date : 2012-10-01 DOI: 10.1109/ESTIMedia.2012.6507026

Shin-Haeng Kang, Hoeseok Yang, Lars Schor, Iuliana Bacivarov, S. Ha, L. Thiele

引用次数: 38

Keynote: “Design space exploration and run-time resource management in the embedded multi-core era” 主题演讲:嵌入式多核时代的设计空间探索与运行时资源管理

2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia Pub Date : 2012-10-01 DOI: 10.1109/ESTIMedia.2012.6507017

V. Zaccaria

{"title":"Keynote: “Design space exploration and run-time resource management in the embedded multi-core era”","authors":"V. Zaccaria","doi":"10.1109/ESTIMedia.2012.6507017","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2012.6507017","url":null,"abstract":"It is widely understood that the next revolution of virtual platform-based design is the holistic optimization of hardware parameters, task mapping and scheduling, and application tuning for many-cores. As a community, we have learned that finding the best trade-off in terms of selected figures of merit can be achieved only by considering the integrated hardware and software dimensions, by evaluating an enormous number of configurations, each characterized by a long simulation time. The problem worsens when dealing with small ecosystems such as embedded systems-on-chip where the environment is too constrained to assume that a sophisticated run-time algorithm can be implemented to schedule efficiently the access to resources. In this keynote I will explain why some newest findings in global optimization can be used to address effectively virtual-platform design. I am going then to describe how sophisticated algorithms based on response-surface prediction models can efficiently identify optimal configurations in a significant number of platform optimization scenarios. Finally, I am going to outline some research directions stemming from the MULTICUBE and 2PARMA EU projects that I think will untap the full potential of platform optimization.","PeriodicalId":431615,"journal":{"name":"2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129942174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Towards real-time applications in mobile web browsers 面向移动web浏览器的实时应用程序

2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia Pub Date : 2012-10-01 DOI: 10.1109/ESTIMedia.2012.6507030

E. Aho, Kimmo Kuusilinna, T. Aarnio, Janne Pietiainen, Jari Nikara

引用次数: 6

Power versus quality trade-offs for adaptive real-time applications 自适应实时应用的功率与质量权衡

2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia Pub Date : 2012-10-01 DOI: 10.1109/ESTIMedia.2012.6507032

Andrew Nelson, B. Akesson, A. Molnos, Sj Pas, K. Goossens

{"title":"Power versus quality trade-offs for adaptive real-time applications","authors":"Andrew Nelson, B. Akesson, A. Molnos, Sj Pas, K. Goossens","doi":"10.1109/ESTIMedia.2012.6507032","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2012.6507032","url":null,"abstract":"Electronic devices are expected to accommodate evermore complex functionality. Portable devices, such as mobile phones, have experienced a rapid increase in functionality, while at the same time being constrained by the amount of energy that may be stored in their batteries. Dynamic Voltage and Frequency Scaling (DVFS) is a common technique that is used to trade processor speed for a reduction in power consumption. Adaptive applications can reduce their output quality in exchange for a reduction in their execution time. This exchange has been shown to be useful for meeting temporal constraints, but its usefulness for reducing energy/power consumption has not been investigated. In this paper, we present a technique that uses existing DVFS methods to trade a quality decrease for lower power/energy consumption through an intermediary reduction in execution time. Our technique achieves this while meeting soft and/or hard time/energy/power constraints. We demonstrate the applicability of our technique on an adaptive H.263 decoder application, running on a predictable hardware platform that is prototyped on an FPGA. We further contribute an experimental evaluation of the H.263 decoder's scalable mechanisms, in their ability to trade quality for temporal/energy/power. From experimentation, we show that our quality trading technique is able to achieve up to a 45% increase in the number of frames decoded for the same amount of energy, in comparison to frequency scaling alone, but with a quality reduction of up to 22dB Peak Signal-to-Noise Ratio (PSNR).","PeriodicalId":431615,"journal":{"name":"2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116961484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays 具有PV和电容器阵列的能量收集嵌入式系统的I/O感知任务调度

2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia Pub Date : 2012-10-01 DOI: 10.1109/ESTIMedia.2012.6507028

Kyungsoo Lee, T. Ishihara

引用次数: 2

Memory-centric VDF graph transformations for practical FPGA implementation 以内存为中心的VDF图形转换的实际FPGA实现

2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia Pub Date : 2012-10-01 DOI: 10.1109/ESTIMedia.2012.6507023

Matthew Milford, J. McAllister

{"title":"Memory-centric VDF graph transformations for practical FPGA implementation","authors":"Matthew Milford, J. McAllister","doi":"10.1109/ESTIMedia.2012.6507023","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2012.6507023","url":null,"abstract":"Realising memory intensive applications such as image and video processing on FPGA requires creation of complex, multi-level memory hierarchies to achieve real-time performance; however commerical High Level Synthesis tools are unable to automatically derive such structures and hence are unable to meet the demanding bandwidth and capacity constraints of these applications. Current approaches to solving this problem can only derive either single-level memory structures or very deep, highly inefficient hierarchies, leading in either case to one or more of high implementation cost and low performance. This paper presents an enhancement to an existing MC-HLS synthesis approach which solves this problem; it exploits and eliminates data duplication at multiple levels levels of the generated hierarchy, leading to a reduction in the number of levels and ultimately higher performance, lower cost implementations. When applied to synthesis of C-based Motion Estimation, Matrix Multiplication and Sobel Edge Detection applications, this enables reductions in Block RAM and Look Up Table (LUT) cost of up to 25%, whilst simultaneously increasing throughput.","PeriodicalId":431615,"journal":{"name":"2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132509814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1