{"title":"Trustworthy Semantic Web Technologies for Secure Knowledge Management","authors":"B. Thuraisingham, Pranav Parikh","doi":"10.1109/EUC.2008.174","DOIUrl":"https://doi.org/10.1109/EUC.2008.174","url":null,"abstract":"Semantic Web technologies have many applications due to their expressive and reasoning power. At the same time, secure knowledge management is becoming a crucial area for many corporations where the data, information and knowledge including the intellectual property and the expertise in the corporation have to be protected. In this paper we explore the applications of trustworthy semantic Web technologies for secure knowledge management.","PeriodicalId":430277,"journal":{"name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","volume":"31 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129678969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Mobile Agent-Supported Web Services Testing Platform","authors":"Jia Zhang, Di Xu","doi":"10.1109/EUC.2008.194","DOIUrl":"https://doi.org/10.1109/EUC.2008.194","url":null,"abstract":"The Web services technology receives significant momentum in recent years, because it allows people to easily utilize and integrate existing software applications to rapidly create new business services. However, how to ensure the trustworthiness of a Web services-oriented system remains a big challenge. One critical issue is how to test a Web service in an effective and efficient manner. In this paper, we report our design and development of a novel mobile agent-based testing platform oriented to Web services. We seamlessly integrate an existing testing tool (HP LoadRunner) with a mobile agent technology (IBM Aglet) to build a practical environment for testing Web services.","PeriodicalId":430277,"journal":{"name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115248935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Online Signature Verification Algorithm Using Hill-Climbing Method","authors":"D. Muramatsu","doi":"10.1109/EUC.2008.84","DOIUrl":"https://doi.org/10.1109/EUC.2008.84","url":null,"abstract":"Attacks using hill-climbing methods have been reported as a vulnerability of biometric authentication systems. In this paper, the author proposes a robust online signature verification algorithm against attacks using the hill-climbing method. Specifically, the attack considered in this paper is a hill-climbing forged data attack. Artificial forgeries are generated by using the hill-climbing method and the forgeries are input to a target system to be attacked. In order to generate a robust algorithm, the author proposes incorporating the hill-climbing method into an online signature verification algorithm. Preliminary experiments were performed using several online signature databases. The results show that the proposed algorithm improved the performance against this kind of attack. Equal Error Rate (EER) was improved from 88.3% to 1.2% when using a private database for evaluation.","PeriodicalId":430277,"journal":{"name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115810095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Nakano, K. Kawakami, K. Shigemoto, Yuki Kamada, Yasuaki Ito
{"title":"A Tiny Processing System for Education and Small Embedded Systems on the FPGAs","authors":"K. Nakano, K. Kawakami, K. Shigemoto, Yuki Kamada, Yasuaki Ito","doi":"10.1109/EUC.2008.25","DOIUrl":"https://doi.org/10.1109/EUC.2008.25","url":null,"abstract":"The main contribution of this paper is to present a simple, scalable, and portable tiny processing system which can be implemented in various FPGAs. Our processing system includes a 16-bit processor, a cross assembler, and a cross compiler. The 16-bit processor runs in 89 MHz on the Xilinx Spartan-3A family FPGAXC3S700A using 336 out of 5888 slices (5.7%)and in 76 MHz on the Altera Cyclon III family EP3C25F324 using 569 out of 24624 logic elements (2.3%). Every instruction can be executed in only one clock cycle, that is, CPI=1. Using a cross assembler and a cross compiler that we have developed, a C-based language program can be translated into a machine language object code, which can be executed on the 16-bit processor. The source codes of our processing system are very simple and compact. The 16-bit processor is designed by Verilog~HDL using 268 lines, and the cross assembler is written in 38 lines using Perl language. The cross compiler has 23 lines of Flex grammar file for lexical analysis, and 90 lines of Bison grammar file for context analysis and code generation. Hence, our tiny processing system is portable and easy to understand and the function expansion is not difficult. Actually, the tiny processing system has been used for the embedded system course of graduate students as a course material. Further, the 16-bit processor is scalable, that is, the word size can be changed from standard 16 bits. As real-life applications, we have developed a PONG-like mini game and an RSA encryption/decryption system based on the tiny processing system. Therefore, our tiny processing system benefits computer system education and small embedded system development.","PeriodicalId":430277,"journal":{"name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131534101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A GA-based Systematic Message Scheduling Method for Time-Triggered CAN","authors":"Shan Ding, Zhiqiang Xie, Xiaona Yin","doi":"10.1109/EUC.2008.73","DOIUrl":"https://doi.org/10.1109/EUC.2008.73","url":null,"abstract":"CAN has been developed to become the most popular control network solution employed in the automotive industry. Time-triggered CAN (TTCAN), which achieves time-triggered behavior by implementing time-division multiple access on the CAN network standard, is an option that will form the basis of a new generation of advanced safety critical distributed systems. Considering several performance metrics, such as bandwidth utilization, an optimal message schedule must be constructed for a given message set. In this paper, we analyzed differences between sets of messages and constructed system matrix that the schedule is generated based on it. Moreover, an optimization problem is how to make event-triggered messages gain the maximum transmission times by minimizing the transmission times occupied by time-triggered messages. A GA-based systematic message scheduling method is proposed to optimize the scheduling table. We have evaluated the proposed scheduling method using experiments.","PeriodicalId":430277,"journal":{"name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130930859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Xenakis, D. Apostolopoulou, A. Panou, I. Stavrakakis
{"title":"A Qualitative Risk Analysis for the GPRS Technology","authors":"C. Xenakis, D. Apostolopoulou, A. Panou, I. Stavrakakis","doi":"10.1109/EUC.2008.123","DOIUrl":"https://doi.org/10.1109/EUC.2008.123","url":null,"abstract":"This paper presents a qualitative risk analysis of the General Packet Radio Service (GPRS) technology. GPRS presents several essential security weaknesses which may lead to security attacks that can compromise the network operation and the data transfer. We perform a detailed threat analysis by identifying the possible attacks that may result from the GPRS security weaknesses. The analyzed threats are categorized into critical areas of GPRS security exposure and further divided into threats that compromise the availability, confidentiality, integrity, privacy, authorization and authentication of the system. Each threat is associated with a qualitative risk value that incorporates the likelihood of the attack and its potential impact on the system. The understanding gained from the analysis is used to classify the threats in low and high risk threats and define the specific areas of GPRS that require additional security measures.","PeriodicalId":430277,"journal":{"name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125566945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application Specific Low Power ALU Design","authors":"Yu Zhou, Hui Guo","doi":"10.1109/EUC.2008.81","DOIUrl":"https://doi.org/10.1109/EUC.2008.81","url":null,"abstract":"Power consumption is a critical design issue in embedded processor design. One of common components in the processor is the Arithmetic and Logic Unit (ALU). Usually, ALUs are designed with a combinational logic circuit containing a number of functional components for different arithmetic and logic operations. An ALU can be constructed with a tree or a chain structure. Existing approaches to reduce power often achieve power reduction at the cost of increased design complexity, thus resulting in delay and area overheads. In this paper, we present a customization approach for the chain-structure based ALU design by repositioning functional components in the chain. The approach can be easily integrated into a processor design environment to effectively reduce ALU power consumption for a given application. We have applied our approach to a set of benchmarks. Ourexperimental results show that the power savings range from 43.5% to 49.6%; on average, 46.9% of ALU power reduction can be achieved. Most importantly, this achievement is at cost of neither hardware complexity nor processor performance, and the implementation is extremely straightforward.","PeriodicalId":430277,"journal":{"name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124617696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Impact-Oriented Metric for Interference to Network Routing","authors":"Song Huang, Lie-Gen Liu","doi":"10.1109/EUC.2008.142","DOIUrl":"https://doi.org/10.1109/EUC.2008.142","url":null,"abstract":"The measurement of interference intensity is critical to design of network architecture and routing protocol. However, most existing metrics for interference to network routing are based on concrete attack behaviors and error generations, which have restricted their applicable range. In this paper, an impact-oriented metric is proposed for the measurement of interference to network routing. As to networks with capability of multi-path routing, traffic can bypass failed links or nodes by using local redundant resources. The metric check the extent to which the extra paths have been used. During this process, both the amount and the usage probability are taken into account.","PeriodicalId":430277,"journal":{"name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114727263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Control-Flow Checking Using Branch Instructions","authors":"Mostafa Jafari-Nodoushan, S. Miremadi, A. Ejlali","doi":"10.1109/EUC.2008.44","DOIUrl":"https://doi.org/10.1109/EUC.2008.44","url":null,"abstract":"This paper presents a hardware control-flow checking scheme for RISC processor-based systems. This scheme combines two error detection mechanisms to provide high coverage. The first mechanism uses parity bits to detect faults occurring in the opcodes and in the target addresses of branch instructions which lead to erroneous branches. The second mechanism uses signature monitoring to detect errors occurring in the sequential instructions. The scheme is implemented using a watchdog processor for an VHDL model of the LEON2 processor. About 31800 simulation faults were injected into the LEON2 processor. The results show that the error detection coverage is about 99.5% with average detection latency of 7 cycles. The performance loss of presented scheme is about 8.4%.","PeriodicalId":430277,"journal":{"name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123160363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Novel Virtual Grid Experiment Method in MedImGrid","authors":"Ran Zheng, Xiaofei Liao, Hai Jin","doi":"10.1109/EUC.2008.147","DOIUrl":"https://doi.org/10.1109/EUC.2008.147","url":null,"abstract":"During the study of grid projects, a real grid environment or simulated grid is built up for development and experiment normally. But there are some disadvantages such as high cost, complex deployment and configuration, hard management, even conflict among people. A novel virtual grid experiment method with HAL (Hardware Abstraction Level) virtualization technology is presented, which can conquer the disadvantages above and has been used in MedImGrid for the development of medical grid applications. The experiment shows that the method is feasible with low cost, easy configuration and convenient management, so as to increase research efficiency and shorten developing cycle. Furthermore, it can be applied not only in MedImGrid but also in some other grid projects.","PeriodicalId":430277,"journal":{"name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124898807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}