Application Specific Low Power ALU Design

Abstract

Power consumption is a critical design issue in embedded processor design. One of common components in the processor is the Arithmetic and Logic Unit (ALU). Usually, ALUs are designed with a combinational logic circuit containing a number of functional components for different arithmetic and logic operations. An ALU can be constructed with a tree or a chain structure. Existing approaches to reduce power often achieve power reduction at the cost of increased design complexity, thus resulting in delay and area overheads. In this paper, we present a customization approach for the chain-structure based ALU design by repositioning functional components in the chain. The approach can be easily integrated into a processor design environment to effectively reduce ALU power consumption for a given application. We have applied our approach to a set of benchmarks. Ourexperimental results show that the power savings range from 43.5% to 49.6%; on average, 46.9% of ALU power reduction can be achieved. Most importantly, this achievement is at cost of neither hardware complexity nor processor performance, and the implementation is extremely straightforward.