Proceedings of 1994 IEEE Workshop on VLSI Signal Processing最新文献_第2页

Pipelined Wave Digital Filter design for narrow-band sharp-transition digital filters 窄带锐利过渡数字滤波器的流水线波数字滤波器设计

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing Pub Date : 1994-10-26 DOI: 10.1109/VLSISP.1994.574774

Jin-Gyun Chung, K. K. Parhi

{"title":"Pipelined Wave Digital Filter design for narrow-band sharp-transition digital filters","authors":"Jin-Gyun Chung, K. K. Parhi","doi":"10.1109/VLSISP.1994.574774","DOIUrl":"https://doi.org/10.1109/VLSISP.1994.574774","url":null,"abstract":"The finite word-length effects in most IIR digital filters can be improved by realizing the transfer function in terms of a cascade or parallel arrangement of second order filter sections instead of a direct-form realization. However, for narrow-band sharp-transition filters, we still have large roundoff noise problems even with second order sections. In this case, the WDF (Wave Digital Filter) can be a good solution. Although the WDFs can be pipelined by the cut-set localization procedure, the maximum sample rate cannot be increased by this technique due to the presence of the feedback loops in the WDFs. In this paper, a pipelined WDF design method for narrow-band sharp transition filters is proposed. The pipelining method is based on the DIFIR (Decomposed and Interpolated FIR) method, where an IIR filter with M-times wider transition bandwidth (compared with the original specification) is cascaded with log/sub 2/ M FIR filters which have very wide transition bandwidths. The new IIR filter produces much smaller noise. In addition, the new IIR transfer function satisfies the pipelining property which can be used in high speed or low power applications.","PeriodicalId":427356,"journal":{"name":"Proceedings of 1994 IEEE Workshop on VLSI Signal Processing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124917937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Low power design of memory intensive functions. Case study: vector quantization 低功耗设计的内存密集型功能。案例研究:矢量量化

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing Pub Date : 1994-10-26 DOI: 10.1109/VLSISP.1994.574762

D. Lidsky, J. Rabaey

引用次数: 29

Digital automatic gain control for hearing aids 数字自动增益控制助听器

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing Pub Date : 1994-10-26 DOI: 10.1109/VLSISP.1994.574725

P. Camilleri, G. Sobelman

引用次数: 2

Microphone array signal processing for hearing aid application 用于助听器的麦克风阵列信号处理

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing Pub Date : 1994-10-26 DOI: 10.1109/VLSISP.1994.574726

D. Korompis, K. Yao, R. E. Hudson, F. Lorenzelli

引用次数: 9

Processor-optimal implementation of real-time DSP algorithms 处理器优化实现实时DSP算法

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing Pub Date : 1994-10-26 DOI: 10.1109/VLSISP.1994.574741

Y. Hu, Duen-Jeng Wang

引用次数: 0

Improved scheduling of signal flow graphs onto multiprocessor systems through an accurate network modelling technique 通过精确的网络建模技术，改进了多处理器系统上信号流图的调度

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing Pub Date : 1994-10-26 DOI: 10.1109/VLSISP.1994.574740

S. Banerjee, D. Picker, R. Fellman, P. Chau

{"title":"Improved scheduling of signal flow graphs onto multiprocessor systems through an accurate network modelling technique","authors":"S. Banerjee, D. Picker, R. Fellman, P. Chau","doi":"10.1109/VLSISP.1994.574740","DOIUrl":"https://doi.org/10.1109/VLSISP.1994.574740","url":null,"abstract":"This paper presents a new integrated technique for accurately scheduling acyclic precedence expansion graphs (APEGs) onto multiprocessor networks with various topologies. APEGs specify the nature, connectivity, and precedence relationships of all tasks, as well as data amounts that pass between tasks. We present a scheduling algorithm that uses the Branch and Bound technique when the number of tasks in the graph is small, and the Earliest Task First heuristic, otherwise. Graph partitioning and scheduling algorithms however, require a good estimate of interprocessor communication (IPC) costs within the target network. We thus use a technique called Successive Superposition to accurately determine IPC costs. Successive Superposition provides a methodology to decompose a complex network, containing primarily deterministic traffic, into simpler queueing models which may then be analyzed in isolation. By combining a heuristic scheduling algorithm with this exact IPC analysis technique, we avoid unpredictable behavior and incorrect mapping decisions that could result in longer graph execution times. We present an example in which an inaccurate assessment of IPC costs leads to a 22% to 30% increase in the graph execution time.","PeriodicalId":427356,"journal":{"name":"Proceedings of 1994 IEEE Workshop on VLSI Signal Processing","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132949161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

A parallel system for photo realistic artificial scene rendering 一种用于照片逼真人工场景渲染的并行系统

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing Pub Date : 1994-10-26 DOI: 10.1109/VLSISP.1994.574767

E. Deprettere, G.H. Hekstra, Li-Shen Sheng, J. Bu, G. Boersma

引用次数: 2

HLS based DSP optimization with ASIC RTL libraries 基于HLS的DSP优化与ASIC RTL库

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing Pub Date : 1994-10-26 DOI: 10.1109/VLSISP.1994.574746

J. Isoaho, J. Oberg, A. Hemani, H. Tenhunen

引用次数: 5

Techniques for at-speed testing of VLSI ASIC designs VLSI ASIC设计的高速测试技术

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing Pub Date : 1994-10-26 DOI: 10.1109/VLSISP.1994.574748

S. Dey, M. Potkonjak

引用次数: 0

A VLSI architecture for modified frequency sensitive self-organizing neural network for image data compression 一种用于图像数据压缩的改进频率敏感自组织神经网络的VLSI结构

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing Pub Date : 1994-10-26 DOI: 10.1109/VLSISP.1994.574766

L. Chiou, J. Limqueco, M. Bayoumi

引用次数: 0