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Proceedings of the 24th European Solid-State Circuits Conference最新文献

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A low-power and high-performance CMOS fingerprint sensing and encoding architecture 一种低功耗、高性能的CMOS指纹传感与编码架构
Proceedings of the 24th European Solid-State Circuits Conference Pub Date : 1999-07-01 DOI: 10.1109/ESSCIR.1998.186274
Stefan Jung, R. Thewes, T. Scheiter, K. Goser, W. Weber
{"title":"A low-power and high-performance CMOS fingerprint sensing and encoding architecture","authors":"Stefan Jung, R. Thewes, T. Scheiter, K. Goser, W. Weber","doi":"10.1109/ESSCIR.1998.186274","DOIUrl":"https://doi.org/10.1109/ESSCIR.1998.186274","url":null,"abstract":"A capacitive fingerprint sensor array with pixel-parallel cellular logic in CMOS is presented. The system acquires a binary fingerprint image and performs several image processing algorithms, including thinning the ridges of the fingerprint structure and extracting its characteristic features. The massive parallelism of the architecture leads to a very low power dissipation. Results of both simulations and measurements on a demonstrator chip are shown. The approach is well suited for person identification applications, especially in small portable systems, such as smart cards.","PeriodicalId":427187,"journal":{"name":"Proceedings of the 24th European Solid-State Circuits Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121740022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 75
A 1.9GHz 1W CMOS class E power amplifier for wireless communications 一种用于无线通信的1.9GHz 1W CMOS E类功率放大器
Proceedings of the 24th European Solid-State Circuits Conference Pub Date : 1999-07-01 DOI: 10.1109/ESSCIR.1998.186212
King-Chun Tsai, P. Gray
{"title":"A 1.9GHz 1W CMOS class E power amplifier for wireless communications","authors":"King-Chun Tsai, P. Gray","doi":"10.1109/ESSCIR.1998.186212","DOIUrl":"https://doi.org/10.1109/ESSCIR.1998.186212","url":null,"abstract":"A CMOS implementation of a Class E power amplifier for wireless communications which operates in the GHz region is reported. The concept of mode-locking is introduced in which the amplifier acts as an oscillator whose output is forced to run at the input frequency. A prototype was built, which delivered over 1W of output power with 48% power added efficiency, centred at 1.9GHz using a 2V supply.","PeriodicalId":427187,"journal":{"name":"Proceedings of the 24th European Solid-State Circuits Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133291966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 314
Reduction of intrinsic 1/f device noise in a CMOS ring oscillator CMOS环形振荡器内禀1/f器件噪声的降低
Proceedings of the 24th European Solid-State Circuits Conference Pub Date : 1998-09-30 DOI: 10.1109/ESSCIR.1998.186261
S. Gierkink, E. Klumperink, T. Ikkink, A.J.M. van Tuijl
{"title":"Reduction of intrinsic 1/f device noise in a CMOS ring oscillator","authors":"S. Gierkink, E. Klumperink, T. Ikkink, A.J.M. van Tuijl","doi":"10.1109/ESSCIR.1998.186261","DOIUrl":"https://doi.org/10.1109/ESSCIR.1998.186261","url":null,"abstract":"The implications of intrinsic 1/f device noise reduction in MOS transistors due to periodic on-off switching in a CMOS ring oscillator are explored. It is shown that maximising the amplitude of oscillation helps to reduce the close-in phase noise. Measurement results, corrected for amplitude-dependent upconversion and effective bias show an improvement of 8 dB in phase noise at 1KHz frequency offset from the carrier at 4.5 dB increase in carrier power.","PeriodicalId":427187,"journal":{"name":"Proceedings of the 24th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129465490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 16-bit D/A interface with sinc approximated semidigital reconstruction filter and reduced number of coefficients 一个16位的D/A接口，带有正弦近似半数字重构滤波器和减少的系数数
Proceedings of the 24th European Solid-State Circuits Conference Pub Date : 1998-09-30 DOI: 10.1109/ESSCIR.1998.186238
M. Sanduleanu, A.J.M. van Tuijl, R. Wassenaar, H. Wallinga
{"title":"A 16-bit D/A interface with sinc approximated semidigital reconstruction filter and reduced number of coefficients","authors":"M. Sanduleanu, A.J.M. van Tuijl, R. Wassenaar, H. Wallinga","doi":"10.1109/ESSCIR.1998.186238","DOIUrl":"https://doi.org/10.1109/ESSCIR.1998.186238","url":null,"abstract":"Due to components nonidealities, the analog reconstruction is the most difficult analog building block in a D/A converter. The paper presents a 16-bit D/A interface with a current driven semidigital filter and reduced number of coefficients. To optimise the number of coefficients an iterative method based on Sinc approximation has been used. With only 25 coefficients we get more than 50dB stopband rejection of noise. A differential solution is proposed to reduce the digital crosstalk and to increase the output swing. The D/A interface has been realised on chip in a 0.8µm CMOS 5V technology. S/N+THD measurements are provided.","PeriodicalId":427187,"journal":{"name":"Proceedings of the 24th European Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133297833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Current–ratio temperature compensation in bipolar relaxation oscillator 双极弛豫振荡器的电流&#8211
Proceedings of the 24th European Solid-State Circuits Conference Pub Date : 1998-09-30 DOI: 10.1109/ESSCIR.1998.186291
M. H. Splithof, A.J.M. van Tuijl, S. Gierkink, E. Klumperink
{"title":"Current–ratio temperature compensation in bipolar relaxation oscillator","authors":"M. H. Splithof, A.J.M. van Tuijl, S. Gierkink, E. Klumperink","doi":"10.1109/ESSCIR.1998.186291","DOIUrl":"https://doi.org/10.1109/ESSCIR.1998.186291","url":null,"abstract":"A new temperature compensation strategy for bipolar relaxation oscillators is presented. The compensation scheme is suitable for both Schmitt-trigger oscillators and emitter-coupled multivibrators and requires a minimum amount of circuitry for the compensation. The feasibility of this compensation scheme is demonstrated by the results of a test chip. Without any trimming and with a total current consumption of 2.5mA, a temperature coefficient of approximately -90ppm/°C has been achieved at frequencies up to 2.5MHz.","PeriodicalId":427187,"journal":{"name":"Proceedings of the 24th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133393201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low-cost all-polymer integrated circuits 低成本全聚合物集成电路
Proceedings of the 24th European Solid-State Circuits Conference Pub Date : 1998-07-01 DOI: 10.1109/ESSCIR.1998.186203
C. M. Hart, D. Leeuw, M. Matters, P. Herwig, C.M.J. Mutsaerts, Christopher J. Drury
{"title":"Low-cost all-polymer integrated circuits","authors":"C. M. Hart, D. Leeuw, M. Matters, P. Herwig, C.M.J. Mutsaerts, Christopher J. Drury","doi":"10.1109/ESSCIR.1998.186203","DOIUrl":"https://doi.org/10.1109/ESSCIR.1998.186203","url":null,"abstract":"A technology has been developed to make all-polymer integrated circuits. It involves reproducible fabrication of field-effect transistors in which the semiconducting, conducting and insulating parts are all made of polymers. The fabrication on flexible substrates uses spin-coating of electrically active precursors and patternwise exposure of the deposited films. In the whole process stack-integrity is maintained. Vertical interconnects are made mechanically. As a demonstrator for the technology functional 15-bit programmable code generators are fabricated. These circuits still operate when the foils are sharply bent. Due to the limited number of process steps the technology is potentially inexpensive.","PeriodicalId":427187,"journal":{"name":"Proceedings of the 24th European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114438608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 739
A multimedia-oriented embedded RISC processor with a rambus DRAM controller 一种具有rambus DRAM控制器的面向多媒体的嵌入式RISC处理器
Proceedings of the 24th European Solid-State Circuits Conference Pub Date : 1900-01-01 DOI: 10.1109/ESSCIR.1998.186229
K. Suzuki, M. Daito, T. Inoue, K. Naehara, M. Nomura, T. Iima, T. Fukuda
{"title":"A multimedia-oriented embedded RISC processor with a rambus DRAM controller","authors":"K. Suzuki, M. Daito, T. Inoue, K. Naehara, M. Nomura, T. Iima, T. Fukuda","doi":"10.1109/ESSCIR.1998.186229","DOIUrl":"https://doi.org/10.1109/ESSCIR.1998.186229","url":null,"abstract":"We have developed a 0.25-µm 200-MHz embedded RISC processor for multimedia applications. This processor has a dual-issue superscaler datapath that consists of a 32-bit integer unit and a 64-bit SIMD function unit, and it achieves 2000-MOPS performance. An on-chip Concurrent Rambus DRAM (C-RDRAM) controller increases memory bandwidth to 533 Mbyte/s through the Rambus channel using interleaved transaction. The controller also reduces latency using the transaction interleaving and instruction prefetching. A 64-bit 200-MHz internal bus transmits the data between the CPU core, the C-RDRAM, and the peripherals. These high-data-rate channels increase the performance of the CPU because they eliminate a bottleneck in the data supply.","PeriodicalId":427187,"journal":{"name":"Proceedings of the 24th European Solid-State Circuits Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116990488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High efficiency charge pump circuit for negative high voltage generation at 2 V supply voltage 高效电荷泵电路，用于在2v电源电压下产生负高压
Proceedings of the 24th European Solid-State Circuits Conference Pub Date : 1900-01-01 DOI: 10.1109/ESSCIR.1998.186218
M. Bloch, C. Lauterbauch, W. Weber
{"title":"High efficiency charge pump circuit for negative high voltage generation at 2 V supply voltage","authors":"M. Bloch, C. Lauterbauch, W. Weber","doi":"10.1109/ESSCIR.1998.186218","DOIUrl":"https://doi.org/10.1109/ESSCIR.1998.186218","url":null,"abstract":"A charge pump circuit has been developed for the generation of negative high voltage at supply voltage levels down to 2V. The generated high voltage is suitable for programming Flash EEPROM cells, that use Fowler-Nordheim tunneling. The key issue of the circuit design has been high efficiency and small chip area. The circuit consists of n-MOS transfer gates in a triple-well structure and is driven by a four phase clocking scheme. The power efficiency of a charge pump, designed for low power applications, is better than 25% at an output power of 100µW, including clock generation and voltage regulation.","PeriodicalId":427187,"journal":{"name":"Proceedings of the 24th European Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124856876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
The future of communications 通信的未来
Proceedings of the 24th European Solid-State Circuits Conference Pub Date : 1900-01-01 DOI: 10.1109/ESSCIR.1998.186204
J. Danneels
{"title":"The future of communications","authors":"J. Danneels","doi":"10.1109/ESSCIR.1998.186204","DOIUrl":"https://doi.org/10.1109/ESSCIR.1998.186204","url":null,"abstract":"Today the telecommunications community is going through a tremendous revolution that will shape the next century. The network will be everywhere and computing will shift from professional desktop computing towards consumer oriented networked computing using compact wireless personal multi-media devices that can communicate with each other as well as with machines such as house hold appliances. Radically new man-machine interfaces will appear and sooner then you think you will be talking to your VCR over your mobile handset in order to program it. Deregulation and convergence are today's magic words. Because of the monopolies, market share used be to guaranteed. Deregulation made competition reenter the game. Today it are consumers that drive the telecommunications market and no longer the governments. In stead of 5-year plans we now have to plan the annual christmas sales and be sure that our prices are competitive. Nowadays, we have to buy market share through time-to-market, price and of course... good products. Network convergence is key to make it all happen. Fixed/mobile and voice/data/video convergence will be essential for the development of the networked society.","PeriodicalId":427187,"journal":{"name":"Proceedings of the 24th European Solid-State Circuits Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116078785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 10b 50–msample/s CMOS ADC in ASIC process ASIC制程中的10b50 –msample/s CMOS ADC
Proceedings of the 24th European Solid-State Circuits Conference Pub Date : 1900-01-01 DOI: 10.1109/ESSCIR.1998.186256
A. Wada, K. Tani, K. Kato, H. Shimizu
{"title":"A 10b 50–msample/s CMOS ADC in ASIC process","authors":"A. Wada, K. Tani, K. Kato, H. Shimizu","doi":"10.1109/ESSCIR.1998.186256","DOIUrl":"https://doi.org/10.1109/ESSCIR.1998.186256","url":null,"abstract":"We have developed a 2-step interstage amplifying pipeline system and new circuit technologies for residue amplifiers. With these techniques, we developed a 50 Msample/s 10b CMOS ADC with a 3.3V power supply, In 0.35µm 1-poly 2-Metal ASIC process without a special analog process. This CMOS ADC measures 4.84mm2. The first test chip was fabricated to verify the new architecture and was measured. It shows good linearity of less than ±1LSB and 130mW power consumption at 50MHz sampling.","PeriodicalId":427187,"journal":{"name":"Proceedings of the 24th European Solid-State Circuits Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122740011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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