A low-power and high-performance CMOS fingerprint sensing and encoding architecture

Abstract

A capacitive fingerprint sensor array with pixel-parallel cellular logic in CMOS is presented. The system acquires a binary fingerprint image and performs several image processing algorithms, including thinning the ridges of the fingerprint structure and extracting its characteristic features. The massive parallelism of the architecture leads to a very low power dissipation. Results of both simulations and measurements on a demonstrator chip are shown. The approach is well suited for person identification applications, especially in small portable systems, such as smart cards.