{"title":"A Fresh Look at Retiming via Clock Skew Optimization","authors":"Sachin S. Sapatnekar Rahul B. Deokar","doi":"10.1109/dac.1995.249965","DOIUrl":"https://doi.org/10.1109/dac.1995.249965","url":null,"abstract":"The introduction of clock skew at an edge-triggered flip-flop has an effect that is similar to the movement of flip-flop across combinational logic module boundaries, and these are continuous and discrete optimizations with the same effect. While this fact has been recognized before, this work, for the first time, utilizes this information to find a minimum/specified period retiming efficiently. The clock period is guaranteed to be at most one gate delay larger than a tight lower bound on the optimal clock period; this bound is achievable using a combination of intentional skew and retiming. All ISCAS89 circuits can be retimed in a few minutes by this algorithm.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134335745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On Test Set Preservation of Retimed Circuits","authors":"A. El-Maleh, T. E. Marchok, J. Rajski, W. Maly","doi":"10.1145/217474.217526","DOIUrl":"https://doi.org/10.1145/217474.217526","url":null,"abstract":"Recently, it has been shown that retiming has a very strong impact on the run time of sequential, structural automatic test pattern generators (ATPGs), as well as the levels of fault coverage and fault efficiency attained. In this paper, we show that retiming preserves testability with respect to a single stuck-at fault test set by adding a prefix sequence of a pre-determined number of arbitrary input vectors. Experimental results show that high fault coverages can be achieved on high performance circuits optimized by retiming with a much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131328052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transient Simulations of Three-dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume approach","authors":"Tom Korsmeyer Mike Chou","doi":"10.1109/dac.1995.249996","DOIUrl":"https://doi.org/10.1109/dac.1995.249996","url":null,"abstract":"It has recently been shown that the boundary-element method can be used to perform accurate cross-talk simulations of three-dimensional integrated circuit interconnect. However, the computational complexity grows as N2, where N is the number of surface unknowns. Straightforward application of the fast-multipole algorithm reduces the computational complexity to order N, but produces magnified errors due to the ill-conditioning of the steady-state problem. We present a mixed surface-volume approach and prove that the formulation results in the exact steady-state solution, independent of the multipole approximations. Numerical experiments are presented to demonstrate the accuracy and efficiency of this technique. On a realistic example, the new method runs fifteen times faster than using dense-matrix iterative methods.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115367944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Requirements-Based Design Evaluation","authors":"S. Frezza, S. Levitan, Panos K. Chrysanthis","doi":"10.1145/217474.217510","DOIUrl":"https://doi.org/10.1145/217474.217510","url":null,"abstract":"This paper presents a methodology for automating the evaluation of partial designs using black-box testing techniques. This methodology generates black-box evaluation tests using a novel semantic graph data model to maintain the relationships between the related design and requirements data. We demonstrate the utility of this technique by using the relationship information to automatically generate and run functionality tests of partial designs against the related requirements.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121615134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Validity of Retiming Sequential Circuits","authors":"V. Singhal, C. Pixley, R. Rudell, R. Brayton","doi":"10.1145/217474.217548","DOIUrl":"https://doi.org/10.1145/217474.217548","url":null,"abstract":"Retiming has been proposed as an optimization step for sequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so changes the number of latches and the longest path delay between the latches. In this paper we show by example that retiming a design may lead to differing simulation results when the retimed design replaces the original design. We also show, by example, that retiming may not preserve the testability of a sequential test sequence for a given stuck-at fault as measured by a simulator. We identify the cause of the problemas forward retiming moves across multiple-fanout points in the circuit. The primary contribution of this paper is to show that, while an accurate logic simulation may distinguish the retimed circuit fromthe original circuit, a conservative three-valued simulator cannot do so. Hence, retiming is a safe operation when used in a design methodology based on conservative three-valued simulation starting each latch with the unknown value.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125971177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Register Allocation and Binding for Low Power","authors":"Jui-Ming Chang, Massoud Pedram","doi":"10.1145/217474.217502","DOIUrl":"https://doi.org/10.1145/217474.217502","url":null,"abstract":"This paper describes a technique for calculating the switching activity of a set of registers shared by different data values. Based on the assumption that the joint pdf (probability density function) of the primary input random variables is known or that a suffficiently large number of input vectors has been given, the register assignment problem for minimum power consumption is formulated as a minimum cost clique covering of an appropriately defined compatibility graph (which is shown to be transitively orientable). The problem is then solved optimally (in polynomial time) using a max-cost ow algorithm. Experimental results confirm the viability and usefulness of the approach in minimizing power consumption during the register assignment phase of the behavioral synthesis process.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126447711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Logic Clause Analysis for Delay Optimization","authors":"B. Rohfleisch, B. Wurth, K. Antreich","doi":"10.1145/217474.217608","DOIUrl":"https://doi.org/10.1145/217474.217608","url":null,"abstract":"In this paper, we present a novel method for topological delay optimization of combinational circuits. Unlike most previous techniques, optimization is performed after technology mapping. Therefore, exact gate delay information is known during optimization. Our method performs incremental network transformations, specifically substitutions of gate input or output signals by new gates. We present new theory which relates incremental network transformations to combinations of global clauses, and show how to detect such valid clause combinations. Employing techniques which originated in the test area, our method is capable to globally optimize large circuits. Comprehensive experimental results show that our method reduces the delay of large standard cell netlists by 23% on average. In contrast to most other delay optimization techniques, area reductions are achieved concurrently.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127505516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-way Partitioning For Minimum Delay For Look-Up Table Based FPGAs","authors":"Prashant S. Sawkar, D. E. Thomas","doi":"10.1145/217474.217530","DOIUrl":"https://doi.org/10.1145/217474.217530","url":null,"abstract":"In this paper we present a set cover based approach (SCP) to multi-way partitioning for minimum delay for Look-Up Table based FPGAs. SCP minimizes the number of chip-crossings on each circuit path with minimum logic duplication costs to achieve implementations with minimum delay and minimum number of chips. The overall complexity of SCP is (V2). Experimental results demonstrate that SCP produces partitions that on the average have 14% fewer chips, 28% fewer pins, and 93% fewer chip-crossings on each circuit path compared to ANN which is a simulated annealing based implementation of classical multi-way partitioning. SCP achieves this performance and compact packing at the cost of duplicating 13% of logic on the average. Additionally, in comparison with a lower bound we observe that SCP has produced near-optimal solutions.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124857873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"System-Level Design for Test of Fully Differential Analog Circuits","authors":"Ramesh Harjani Bapiraju Vinnakota","doi":"10.1109/dac.1995.249989","DOIUrl":"https://doi.org/10.1109/dac.1995.249989","url":null,"abstract":"Analog IC test occupies a significant fraction of the design cycle. Testing costs are increased by the twin requirements of high precision and accuracy in signal measurement. We discuss a system level ACOB technique for fully differential analog ICs. Our test techniques incorporate analog specific constraints such as device matching, and circuit and switching noise. They have a minimal impact on performance, area and power. The techniques can be used for both discrete and continuous time circuits, over a wide frequency range. The system level DFT scheme is also used to design a self-testing switched capacitor filter. Our checking scheme provides significant fault coverage and is demonstrably superior to other DFT techniques for differential circuits.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116684714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Cao, A. Adalal, J. Bauman, P. Delisle, P. Dedood, P. Donehue, M. Dell'OcaKhouja, T. Doan, Manjunath Doreswamy, P. Ferolito, O. Geva, D. Greenhill, S. Gopaladhine, J. Irwin, L. Lev, J. MacDonald, M. Ma, Samir Mitra, P. Patel, A. Prabhu, R. Puranik, S. Rozanski, N. Ross, P. Saggurti, S. Simovich, R. Sunder, B. Sur, W. Vercruysse, M. Wong, P. Yip, R. Yu, J. Zhou, G. Zyner
{"title":"CAD Methodology for the Design of UltraSPARC™ -I Microprocessor at Sun Microsystems Inc.","authors":"A. Cao, A. Adalal, J. Bauman, P. Delisle, P. Dedood, P. Donehue, M. Dell'OcaKhouja, T. Doan, Manjunath Doreswamy, P. Ferolito, O. Geva, D. Greenhill, S. Gopaladhine, J. Irwin, L. Lev, J. MacDonald, M. Ma, Samir Mitra, P. Patel, A. Prabhu, R. Puranik, S. Rozanski, N. Ross, P. Saggurti, S. Simovich, R. Sunder, B. Sur, W. Vercruysse, M. Wong, P. Yip, R. Yu, J. Zhou, G. Zyner","doi":"10.1145/217474.217485","DOIUrl":"https://doi.org/10.1145/217474.217485","url":null,"abstract":"The overall CAD methodology for the design of UltraSPARC-I microprocessor at Sun is described in this paper. Topics discussed include: CAD flow strategy, tool development and integration strategy, and design infrastructure. The importance of concurrent design style, modular CAD flow environment, incremental design verification and early design quality checking is strongly emphasized in this paper.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116852997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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