{"title":"Recognition of Transrectal Ultrasound Prostate Image Based on HOG-LBP","authors":"Xiaofu Huang, Ming Chen, Peizhong Liu","doi":"10.1109/ICASID.2019.8925236","DOIUrl":"https://doi.org/10.1109/ICASID.2019.8925236","url":null,"abstract":"Prostate biopsy is a gold standard for diagnosing prostate cancer. In clinic, multi-needle saturation puncture is often used in the diagnosis of prostate cancer. Although it can improve the positive rate of diagnosis, it also increases the probability of postoperative infection, hematuria and other complications. This paper presents a method to identif prostate cancer by histogram of oriented gradient (HOG) and local binary pattern (LBP) feature extraction. Firstly, Gaussian filtering, gradient transformation function and other algorithms are used to preprocess the transrectal ultrasound prostate images to filter out image noise and improve contrast. Then, the local and global texture feature information of the image is extracted by using HOG and LBP. Finally, support vector machine (SVM) is used to classify features and identify positive regions. The results show that the proposed method is superior to other methods. The transrectal ultrasound prostate images exhibit superior diagnostic performance with an accuracy of 72.2% and a specificity of 75%. Experiments show that this method can provide the necessary auxiliary information for doctor diagnosis and reduce the number of puncture needles.","PeriodicalId":422125,"journal":{"name":"2019 IEEE 13th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"152 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117163798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimized Propagation Algorithm and Layout Hierarchy Reconstruction","authors":"Mingchao Yin, Chun Zhang","doi":"10.1109/icasid.2019.8925002","DOIUrl":"https://doi.org/10.1109/icasid.2019.8925002","url":null,"abstract":"The hierarchy of layout is used to reduce the data amount of layout interchange and store, and also reduce the amount of computation in inevitable processes such as design rule check (DRC) and optical proximity correction (OPC). This paper proposes an optimized propagation algorithm which reduces 40% runtime as to the traditional one at most and devises a novel layout hierarchy reconstruction schema increasing its practicability.","PeriodicalId":422125,"journal":{"name":"2019 IEEE 13th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121865889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Convolutional Neural Network (CNN) Accelerator Chip Design","authors":"Xinran Ma, Ruiyong Zhao, Jianyang Zhou","doi":"10.1109/ICASID.2019.8925182","DOIUrl":"https://doi.org/10.1109/ICASID.2019.8925182","url":null,"abstract":"With the development of artificial intelligence, artificial neural network has been applied in many industry fields. The convolutional neural network (CNN) which is one of the most important algorithms in deep learning plays an important role in computer vision and natural language processing. With machine learning becomes more complex, the amount of data and the amount of computation in CNN increase dramatically. A large amount of data multiplexing consumes a lot of data handling time for the traditional CPU (Von Neumann Architecture and Harvard Architecture). The data processing speed affects the CPU performance. Increasing computation speed and reducing data multiplexing have become the primary goal of neural network accelerators.","PeriodicalId":422125,"journal":{"name":"2019 IEEE 13th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"42 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129659065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Adaptive Echo Cancellation Module for the Same Frequency Repeater Based on LMS Algorithm and FPGA","authors":"Chaodong Ling, Huipeng Duan, Wencai Lin, Ruimin Huang, Hongkai Qin, Qing Tao","doi":"10.1109/ICASID.2019.8924998","DOIUrl":"https://doi.org/10.1109/ICASID.2019.8924998","url":null,"abstract":"To extend the coverage of base stations, the same frequency repeater is widely used in modern communication network. However, there exists coupling echo interference between transmitting antenna and receiving antenna of the repeater station, which affects the system stability and the signal quality. The echo interference is in the same frequency with the useful signals of base stations, which cannot be eliminated by traditional frequency-domain filtering. To address this problem, this paper proposes an adaptive echo cancellation algorithm by inducing an additional reference sequences, which is targeted to apply in the hardware platform of Fujian Jingao FDD-TLE same frequency repeater. In this paper, the working principle of the algorithm is described firstly; then the algorithm is analyzed by MATLAB simulation, and finally verified in FPGA. The comparisons between before and after echo cancellation using the proposed algorithm in time domain and frequency domain shows that this algorithm can effectively suppress echo interference, and the output signal spectrum is significantly improved. Compared with the adaptive filtering algorithm based on the transform domain, this algorithm does not need Fourier transform, which has lower computational complexity and takes less resource. Moreover, this algorithm has a wide application scope and does not depend on the specific modulation scheme of the relaying signal.","PeriodicalId":422125,"journal":{"name":"2019 IEEE 13th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128057424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Juzhe Li, Xu Liu, Jiahui Liu, Di Zhao, Wenrui Yan, Chengju Bi
{"title":"Design of a High-Precision Time-Domain Comparator","authors":"Juzhe Li, Xu Liu, Jiahui Liu, Di Zhao, Wenrui Yan, Chengju Bi","doi":"10.1109/ICASID.2019.8925123","DOIUrl":"https://doi.org/10.1109/ICASID.2019.8925123","url":null,"abstract":"This paper presents a high-speed and high-precision time-domain comparator integrated circuit. The proposed comparator adopts a voltage-controlled oscillator circuit and a time amplifier, to convert the analog input voltage to a phase difference in time domain with high precision. By introducing a feedback for VCO and using the phase detector in the following stage to judge the phase differences between two signals directly, the input signals can be compared in a high speed. The comparator is designed in SMIC $mathbf{0.18 mu m}$ CMOS process technology. The simulation results show that under 1 V power supply, this comparator achieves $mathbf{0.1 mu V}$ accuracy, 181 MHz maximum response speed, and $mathbf{86 mu W}$ power consumption.","PeriodicalId":422125,"journal":{"name":"2019 IEEE 13th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126656140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jie Gao, Chongfei Shen, Baodong Yu, Hongyun Xie, Zhijie Chen, Peiyuan Wan
{"title":"Simulink Modeling and Performance Verification of a High Resolution Zoom ADC","authors":"Jie Gao, Chongfei Shen, Baodong Yu, Hongyun Xie, Zhijie Chen, Peiyuan Wan","doi":"10.1109/ICASID.2019.8925296","DOIUrl":"https://doi.org/10.1109/ICASID.2019.8925296","url":null,"abstract":"This paper presents a Simulink model of a dynamic zoom analog to digital converter (ADC) for use in the field of high resolution sensor readout circuit. The zoom ADC employs a 5-bit asynchronous SAR ADC in the front-end, which dynamically updates the 5-bit DAC references for the following 1-bit second order Sigma-Delta modulator (SDM). Data-weighted averaging (DWA) logic is adopted to alleviate the capacitance mismatch in the 5-bit DAC. The performance of the model is verified by using MATLAB Simulink. The result shows that when the input signal frequency is 150 Hz and the oversampling rate is 1000, the signal-to-noise ratio (SNR) is 127.8 dB, the effective resolution (ENOB) of the system can reach 20.94 bits.","PeriodicalId":422125,"journal":{"name":"2019 IEEE 13th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127310588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Service System Based on Formal Concept Analysis Theory","authors":"Na Wang, Junping Wang, Qi Wei, Lulu Zhao","doi":"10.1109/ICASID.2019.8925005","DOIUrl":"https://doi.org/10.1109/ICASID.2019.8925005","url":null,"abstract":"Formal concept analysis theory is a mathematical tool by establishing formal data structure to express the abstract relationship of concepts at different levels[1], It has absolute advantages in expressing the dependence relationship, which is used to be visualized by Hasse graph, between concept data. Based on this theory, the paper designs and implements a service system, which realizes data analysis and information retrieval. Firstly, the formal context is built in specific field according to the functions. Secondly, formal concept analysis tools are used to construct concept lattices of context and extract association rules. Then, the whole service system is established based on association rules. Finally, the service system is applied to medical treatment, health exercise and academic research to realize the functions of blood test results analysis, human body composition monitoring results analysis, academic research direction retrieval and so on.","PeriodicalId":422125,"journal":{"name":"2019 IEEE 13th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130771124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a New Variable Gain Amplifier","authors":"Juzhe Li, Xu Liu, Di Zhao, Jiahui Liu, Chengju Bi","doi":"10.1109/icasid.2019.8925004","DOIUrl":"https://doi.org/10.1109/icasid.2019.8925004","url":null,"abstract":"This paper proposes a new variable gain amplifier (VGA) using the tunable exponential tail current source. Compared to the traditional digitally controlled VGA where constant tail current source is applied, the proposed design improves the dynamic range due to the larger current provided by the exponential tail current source. Moreover, tail current source array is used in this work to further increase the dynamic range. This new VGA circuit design is completed using SMIC $mathbf{0.18} mumathbf{m}$ CMOS process in Cadence. The simulation results show that the total exponential tail current for each stage ranges from $mathbf{4.7} mu mathbf{A} -279 mu mathbf{A}$, and a dynamic range of −3 dB ~35 dB, with 6.67 MHz bandwidth is achieved.","PeriodicalId":422125,"journal":{"name":"2019 IEEE 13th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128224207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Convergence Batch Dataset Algorithm Based on Deep Learning Model","authors":"Zhining You, Yunming Pu, Hua-fu Zeng","doi":"10.1109/ICASID.2019.8924989","DOIUrl":"https://doi.org/10.1109/ICASID.2019.8924989","url":null,"abstract":"In the training process of deep learning model, GPU is basically used for accelerated training. Batch is a key concept in accelerated training in deep learning. By adjusting and combining the samples in the batch, we seek to ensure that the sample combinations of batch are different and that the sample labels of each batch are the same at each training iteration of the depth model. The algorithm is called CBDA (Convergence Batch Dataset Algorithm). Although the algorithm sacrifices a certain amount of computing time and enlarges the number of iterations, it delays the increase of fitting and improves the generalization of the model. Based on the accepted MNIST dataset, the experimental results confirm the advantages of CBDA.","PeriodicalId":422125,"journal":{"name":"2019 IEEE 13th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133834529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A New Large-Swing Class-AB Buffer Amplifier with High-Driving Enhancement","authors":"Yao Wang, Jianyang Zhou","doi":"10.1109/ICASID.2019.8925204","DOIUrl":"https://doi.org/10.1109/ICASID.2019.8925204","url":null,"abstract":"This brief presents a new type of class-AB buffer amplifier with large-swing and high-driving load capability. It includes two parts, one is a high gain input stage, and the other part is a pseudo source follower which includes a pair of different common source transistors and a pair of different error amplifiers. The gain of the error amplifier can be self-regulated to reduce the variation of quiescent current. This study also provides experimental results obtained from 180 nm CMOS technology.","PeriodicalId":422125,"journal":{"name":"2019 IEEE 13th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115453466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}