2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Growth and fabrication of carbon-based three-dimensional heterostructure in through-silicon vias (TSVs) for 3D interconnects","authors":"Ye Zhu, C. Tan, S. L. Chua, Y. Lim, B. Tay, C. S. Tan","doi":"10.1109/EPTC.2017.8277558","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277558","url":null,"abstract":"Carbon nanomaterials such as graphene and carbon nanotubes (CNTs) have recently received much attention as potential materials proposed for integration in the future semiconductor technologies because of the advantageous properties particularly in thermal and electrical conductivities. Among them, three-dimensional (3D) pillared CNT-graphene nanostructures are especially attractive due to the desirable out-of-plane and in-plane properties. In this work, a growth and fabrication process flow of CNT-graphene heterostructure as filler of TSV for 3D interconnects was designed and explored. First, experiments for the fabrication of top wafer with unfilled TSV of various diameters (5–50μm) and bottom wafer with patterned graphene electrodes and catalyst deposition were completed successfully. Next, top TSV wafer and bottom graphene wafer were bonded and manually ground followed by wet and dry etching to completely remove the handling wafer and buried oxide, exposing the underlying TSV. CNT growth was conducted for both within TSV and free standing on the graphene. Compared to the free-standing growth with sufficient length (∼334μm) and high density (∼1011 cm−2 estimated), few via holes have CNTs grown and none was completely filled by CNTs. The inhibited growth of CNTs within unfilled TSV can possibly be attributed to several process-engineering steps involved in wafer-bonding, grinding and wet/dry etching. Further modification and optimization of the process steps need to be done in order to attain higher CNT fillings within the unfilled TSV.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124208013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low temperature Cu-Cu bonding using tin nanoparticles fabricated by high pressure magnetron sputtering","authors":"Zijian Wu, Qian Wang, Jian Cai","doi":"10.1109/EPTC.2017.8277520","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277520","url":null,"abstract":"A low temperature wafer-level Cu-Cu bonding method using Sn nanoparticles (NP) was proposed and realized in this paper. A bonding structure consisted of Cu bonding pads, TiW barrier/adhesive layer was firstly fabricated on the silicon wafer. Sn NPs were then deposited by high pressure physical vapor deposition (PVD) on Cu pads. The morphology of Sn NPs was studied. Bonding process was successfully proceeded at 200°C for 3min under the pressure of 40MPa. Shear tests were performed after bonding, and the influence of annealing time on shear strength were assessed. The average shear strength without annealing process reached 16.46MPa. Transmission electron microscope (TEM) photos of the fracture interfaces were presented and the energy dispersive X-ray (EDX) analysis of the fracture surfaces showed that Sn has already diffused in Cu. The results mentioned above demonstrated that a robust low temperature short time Cu-Cu bonding was realized by Sn NPs fabricated by PVD.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123319926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive defect monitoring technique for advanced fanout packaging process","authors":"A. Vangai, R. Yeoh, Wesley Chang, ShihLin Pan, Wei-Shen Kuo, A. Pandey, Kevin Khoo, Rahul Lakhawat, Kootz Wang","doi":"10.1109/EPTC.2017.8277583","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277583","url":null,"abstract":"With the latest advances in technology nodes becoming very cost-intensive, the semiconductor industry has focused on cost-saving approaches in the packaging space. Fanout packaging is expected to play an increasingly major role in the coming years. While there have been many published articles on the process integration, this paper focusses on yield and reliability in a production environment. The thesis of this paper is a novel approach to yield monitoring because this is critical to a production environment. Latest advances in this technology have resulted in sophisticated fanout packaging processes, such as the multi-chip module fanout packaging, which requires a front-end like approach to defect monitoring and management. As fanout packaging techniques evolve, process complexity and the number of layers are expected to increase significantly compared to the traditional fan-in packaging [1]. Traditionally, before the onset of fanout production, defect monitoring for packaging typically comprised of inspection on the solder bumps. The major source of defects from a packaging perspective are broken, merged or damaged solder bumps. However, fanout packaging uses metal redistribution layers to electrically connect stacks of layers. Moreover, the dimensions of these redistribution layers range around a few microns to tens of microns. The reliability concerns on the redistribution layers are much more severe as opens, shorts and damages on the redistribution layers impact the overall reliability of the packaged chip. Hence, sensitivity or resolution for defects ranging in the order of microns is an important yardstick to measure yield and reliability accurately in the advanced fanout packaging production space. Hence, there is a need to approach defect management in a structured way to accurately estimate yield and defectivity. In this paper, we will discuss and present a comprehensive high throughput, non-invasive, non-contact defect monitoring strategy for state-of-the-art fanout packaged devices with advanced design rules. We would also further discuss different yield killers as seen through our inspection method. This work is a collaborative project between KLA-Tencor and ASE, Kaohsiung.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124300540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Feasability study of piezo jet printed silver ink structures for interconnection and condition monitoring of power electronics components","authors":"M. Mueller, J. Franke","doi":"10.1109/EPTC.2017.8277552","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277552","url":null,"abstract":"In the field of power electronics, assembly and interconnection technologies play an important role for the design of modules and systems. The applied packaging technologies largely determine the electrical, thermal and mechanical properties of the final module. In addition to conventional solder technology upcoming technologies like sintering, transient liquid phase soldering, adhesive bonding or even reactive multilayer materials are interesting methods for the realization of the die attach. [1] This paper is about a combination of sintering and adhesive bonding for the interconnection of power electronics components. As interconnection material a highly viscous conductive silver ink is used. Additionally also sensor structures were printed with the same silver ink to test the potentials for condition monitoring applications in the field of power electronics.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125705980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Die level 3D heterogeneous integration of a microfluidic system","authors":"N. P. V. Krishna, P. Sen","doi":"10.1109/EPTC.2017.8277519","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277519","url":null,"abstract":"Lab-on-a-chip (LOC) devices has enabled handheld sensing systems for chemical analysis and biological detection. Stacking based integration of various components of an LOC device would lead to system miniaturization and would allow accommodation of more functionalities in a given volume. In this paper, we report a 3D integrated heterogenous system incorporating a silicon photodetector, optical plastic filters, glass microfluidic device and an LED all stacked in 3D and interconnected to function as a fluorescence detection platform. Processing methodology and testing results are reported here.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130135731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Visualization of oxide removal during ultrasonic wire bonding process","authors":"Y. Long, F. Dencker, Andreas Isaak, F. Schneider, J. Hermsdorf, M. Wurz, J. Twiefel","doi":"10.1109/EPTC.2017.8277489","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277489","url":null,"abstract":"As a predominant interconnection technique, ultrasonic wire bonding has been applied in microelectronic packaging industry for decades. However, the bonding mechanisms are still unclear, especially for the oxide removal process. In this work, the whole oxide removal process was visualized by the real-time observations of artificial coated layers. An oxide layer was deposited on either the wire or the glass substrate and a high-speed observation system was focused on the wire/glass interface so that the changes of oxide layer at the interface can be observed. For the coated wire, cracks can be clearly observed after the normal force loading and concentrated at the peripheral contact region. The discretized oxides were then detached from the pure metal surface and rolled into small particles. The oxide particles were transported by the material flow and stress gradient induced compelling. The continuous plastic deformation induced material flow played an important role on the removal of substrate oxides.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134330750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High reliability mid-temperature pb-free alloy for multi-step soldering","authors":"P. Choudhury, M. Ribas, S. Sarkar","doi":"10.1109/EPTC.2017.8277487","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277487","url":null,"abstract":"High silver Sn-Ag-Cu solder alloys, such as Sn-3Ag-0.5Cu (SAC305), result in solder joints with high mechanical and thermal reliability, and can sustain relatively high operational temperatures. However, their melting point (generally above 217°C) requires at least 240–250°C reflow temperatures, putting additional stresses on printed circuit boards. Solder alloys allowing for lower reflow temperatures can be very advantageous, adding benefits such as long-term reliability, lower energy cost and reduced cycle time and enabling multi-step soldering. Here we present our new Pb-free solder alloy that allows for a 25–30°C reduction in peak reflow temperatures. We investigate the effect of various alloying additions into the mechanical properties of three alloys, 1N, 3D and 3E. We also investigate the thermal cycling performance of these alloys when used as solder paste. The results presented here show that solder alloy 3D enables peak reflow temperatures as low as 215°C, in combination with higher mechanical properties and improved fatigue life that is significantly higher than SAC305.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133285003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Review on test vehicles for electromigration (EM) study in solder interconnects","authors":"Ze‐Lin Zhu, Y. Chan, Fengshun Wu, C. Gan, Zhong Chen","doi":"10.1109/EPTC.2017.8277478","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277478","url":null,"abstract":"The reliability of electronic devices faces the challenges of potential open and short failures due to electromigration (EM) in integrated circuit. This issue is becoming more severe at the background of further miniaturization in solder joint size and higher current carried by solder joint. Various test vehicles have been put forward for EM study. This work summarized the EM test vehicles according to the fabrication complexity and development history, and sorted into four categories: flip chip (FC) interconnect, wire-type interconnect, thin-film interconnect and liquid-phase interconnect. The advantages and disadvantages of these typical test vehicles are carefully compared. Due to the mature process, the test vehicles with FC interconnect can be fabricated with solder joints in uniform size. However, the unique geometric asymmetry induces serious current crowding in the entrance and exit of the joint. The test vehicles with wire-type interconnect are often limited in miniaturizing the dimensions due to the mechanical process in fabricating wires. The thin-film interconnect can adjust the dimensions by controlling the electroplating time, wherever the time to prepare the test vehicle can be much longer. A multi-lines thin-film test vehicle has been proposed to study the effect of EM on the microstructure evolution as well as the lifetime prediction. The liquid phase interconnect with synchrotron radiation facility provides real-time and in-situ observation of EM effect.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133425623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of NFC WISP system for wearable devices","authors":"Xuesong Zhang, Qian Wang, H. Guo, Yu Chen, Jian Cai","doi":"10.1109/EPTC.2017.8277482","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277482","url":null,"abstract":"Wearable devices are developing rapidly recent years in multiple areas such as continuous monitoring of human vital signs including body temperature, blood pressure, electrocardiogram, and blood glucose. The increased integration level for wearable devices has proposed higher request for power sources. Conventional button cell has become bulky for epidermal and implantable medical sensing. Wireless power delivery employing RFID technology including near field communication (NFC) is a common solution in such a case. In this paper some related problems for NFC technology such as coil inductor coupling and inductor geometry optimization is discussed and simulated with HFSS. A circuit board of wireless identification and sensing platform (WISP) is designed; experiences for functional test are given out. A wearable sensor system including a NFC interface chip AS3953, a low power MSP430 MCU, a spiral inductor, and a thermometer sensor for human body temperature measurement is proposed with flexible integration by Fan-out WLP procedures.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132691306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of chip-first and die-up fan-out wafer level packaging","authors":"X. Hua, Hong Xu, Li Zhang, Dong Chen, K. Tan, C. Lai, J. Lau, Ming Li, Margie Li, E. Kuah, N. Fan, Wu Kai, Ken Cheung","doi":"10.1109/EPTC.2017.8277553","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277553","url":null,"abstract":"This study is for fan-out wafer-level packaging (FOWLP) with chip-first and die-up processing. The chips with Cu contact pads on the front-side and a die attach film on the backside are picked and placed face-up on a temporary glass carrier with a layer of light-to-heat conversion material. It is followed by compression molding with epoxy molding compound (EMC) and post mold cure (PMC) on the reconstituted wafer carrier, and then backgrinding the molded EMC to expose the Cu contact pads (Cu revealing) of the chips. The next step is to build up the redistribution layers (RDLs) from the contact pads and then mount the solder balls. Next comes the de-bonding of the carrier with a laser, and then the dicing of the whole reconstituted molded wafer into individual packages.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115514821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}