2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第2页

Security for Safety: A Path Toward Building Trusted Autonomous Vehicles 安全保障:打造可信赖的自动驾驶汽车之路

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2018-11-05 DOI: 10.1145/3240765.3243496

R. Dutta, Feng Yu, Teng Zhang, Yaodan Hu, Yier Jin

{"title":"Security for Safety: A Path Toward Building Trusted Autonomous Vehicles","authors":"R. Dutta, Feng Yu, Teng Zhang, Yaodan Hu, Yier Jin","doi":"10.1145/3240765.3243496","DOIUrl":"https://doi.org/10.1145/3240765.3243496","url":null,"abstract":"Automotive systems have always been designed with safety in mind. In this regard, the functional safety standard, ISO 26262, was drafted with the intention of minimizing risk due to random hardware faults or systematic failure in design of electrical and electronic components of an automobile. However, growing complexity of a modern car has added another potential point of failure in the form of cyber or sensor attacks. Recently, researchers have demonstrated that vulnerability in vehicle's software or sensing units could enable them to remotely alter the intended operation of the vehicle. As such, in addition to safety, security should be considered as an important design goal. However, designing security solutions without the consideration of safety objectives could result in potential hazards. Consequently, in this paper we propose the notion of security for safety and show that by integrating safety conditions with our system-level security solution, which comprises of a modified Kalman filter and a Chi-squared detector, we can prevent potential hazards that could occur due to violation of safety objectives during an attack. Furthermore, with the help of a car-following case study, where the follower car is equipped with an adaptive-cruise control unit, we show that our proposed system-level security solution preserves the safety constraints and prevent collision between vehicle while under sensor attack.","PeriodicalId":413037,"journal":{"name":"2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129260178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

DATC RDF: An Academic Flow from Logic Synthesis to Detailed Routing DATC RDF:从逻辑综合到详细路由的学术流程

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2018-11-05 DOI: 10.1145/3240765.3272126

Jinwook Jung, I. Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam

引用次数: 12

Property Specific Information Flow Analysis for Hardware Security Verification 硬件安全验证的属性特定信息流分析

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2018-11-05 DOI: 10.1145/3240765.3240839

Wei Hu, Armaiti Ardeshiricham, Mustafa S. Gobulukoglu, Xinmu Wang, R. Kastner

引用次数: 6

Optimizing Data Layout and System Configuration on FPGA-based Heterogeneous Platforms 基于fpga的异构平台数据布局和系统配置优化

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2018-11-05 DOI: 10.1145/3240765.3240834

H. Ko, Zhiyuan Li, S. Midkiff

引用次数: 1

C-GOOD: C-code Generation Framework for Optimized On-device Deep Learning C-GOOD:优化设备上深度学习的c代码生成框架

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2018-11-05 DOI: 10.1145/3240765.3240786

Duseok Kang, Euiseok Kim, Inpyo Bae, Bernhard Egger, S. Ha

{"title":"C-GOOD: C-code Generation Framework for Optimized On-device Deep Learning","authors":"Duseok Kang, Euiseok Kim, Inpyo Bae, Bernhard Egger, S. Ha","doi":"10.1145/3240765.3240786","DOIUrl":"https://doi.org/10.1145/3240765.3240786","url":null,"abstract":"Executing deep learning algorithms on mobile embedded devices is challenging because embedded devices usually have tight constraints on the computational power, memory size, and energy consumption while the resource requirements of deep learning algorithms achieving high accuracy continue to increase. Thus it is typical to use an energy-efficient accelerator such as mobile GPU, DSP array, and customized neural processor chip. Moreover, new deep learning algorithms that aim to balance accuracy, speed, and resource requirements are developed on a deep learning framework such as Caffe[16] and Tensorflow[1] that is assumed to run directly on the target hardware. However, embedded devices may not be able to run those frameworks directly due to hardware limitations or missing OS support. To overcome this difficulty, we develop a deep learning software framework that generates a C code that can be run on any devices. The framework is facilitated with various options for software optimization that can be performed according to the optimization methodology proposed in this paper. Another benefit is that it can generate various styles of C code, tailored for a specific compiler or the accelerator architecture. Experiments on three platforms, NVIDIA Jetson TX2[23], Odroid XU4[10], and SRP (Samsung Reconfigurable Processor)[32], demonstrate the potential of the proposed approach.","PeriodicalId":413037,"journal":{"name":"2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115492482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Canonicalization of Threshold Logic Representation and Its Applications 阈值逻辑表示的规范化及其应用

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2018-11-05 DOI: 10.1145/3240765.3240785

Siang-Yun Lee, Nian-Ze Lee, J. H. Jiang

{"title":"Canonicalization of Threshold Logic Representation and Its Applications","authors":"Siang-Yun Lee, Nian-Ze Lee, J. H. Jiang","doi":"10.1145/3240765.3240785","DOIUrl":"https://doi.org/10.1145/3240765.3240785","url":null,"abstract":"Threshold logic functions gain revived attention due to their connection to neural networks employed in deep learning. Despite prior endeavors in the characterization of threshold logic functions, to the best of our knowledge, the quest for a canonical representation of threshold logic functions in the form of their realizing linear inequalities remains open. In this paper we devise a procedure to canonicalize a threshold logic function such that two threshold logic functions are equivalent if and only if their canonicalized linear inequalities are the same. We further strengthen the canonicity to ensure that symmetric variables of a threshold logic function receive the same weight in the canonicalized linear inequality. The canonicalization procedure invokes $O(m)$ queries to a linear programming (resp. an integer linear programming) solver when a linear inequality solution with fractional (resp. integral) weight and threshold values is to be found, where $m$ is the number of symmetry groups of the given threshold logic function. The guaranteed canonicity allows direct application to the classification of NP (input negation, input permutation) and NPN (input negation, input permutation, output negation) equivalence of threshold logic functions. It may thus enable applications such as equivalence checking, Boolean matching, and library construction for threshold circuit synthesis.","PeriodicalId":413037,"journal":{"name":"2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125391537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

SODA: Stencil with Optimized Dataflow Architecture SODA:具有优化数据流架构的模板

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2018-11-05 DOI: 10.1145/3240765.3240850

Yuze Chi, J. Cong, Peng Wei, Peipei Zhou

{"title":"SODA: Stencil with Optimized Dataflow Architecture","authors":"Yuze Chi, J. Cong, Peng Wei, Peipei Zhou","doi":"10.1145/3240765.3240850","DOIUrl":"https://doi.org/10.1145/3240765.3240850","url":null,"abstract":"Stencil computation is one of the most important kernels in many application domains such as image processing, solving partial differential equations, and cellular automata. Many of the stencil kernels are complex, usually consist of multiple stages or iterations, and are often computation-bounded. Such kernels are often offloaded to FPGAs to take advantages of the efficiency of dedicated hardware. However, implementing such complex kernels efficiently is not trivial, due to complicated data dependencies, difficulties of programming FPGAs with RTL, as well as large design space. In this paper we present SODA, an automated framework for implementing Stencil algorithms with Optimized Dataflow Architecture on FPGAs. The SODA microarchitecture minimizes the on-chip reuse buffer size required by full data reuse and provides flexible and scalable fine-grained parallelism. The SODA automation framework takes high-level user input and generates efficient, high-frequency dataflow implementation. This significantly reduces the difficulty of programming FPGAs efficiently for stencil algorithms. The SODA design-space exploration framework models the resource constraints and searches for the performance-optimized configuration with accurate models for post-synthesis resource utilization and on-board execution throughput. Experimental results from on-board execution using a wide range of benchmarks show up to 3.28x speed up over 24-thread CPU and our fully automated framework achieves better performance compared with manually designed state-of-the-art FPGA accelerators.","PeriodicalId":413037,"journal":{"name":"2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130013845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 71

IC/IP Piracy Assessment of Reversible Logic 可逆逻辑的IC/IP盗版评估

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2018-11-05 DOI: 10.1145/3240765.3240817

S. Saeed, Xiaotong Cui, Alwin Zulehner, R. Wille, R. Drechsler, Kaijie Wu, R. Karri

引用次数: 8

FCN-Engine: Accelerating Deconvolutional Layers in Classic CNN Processors FCN-Engine:经典CNN处理器中的加速反卷积层

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2018-11-05 DOI: 10.1145/3240765.3240810

Dawen Xu, Kaijie Tu, Y. Wang, Cheng Liu, Bingsheng He, Huawei Li

{"title":"FCN-Engine: Accelerating Deconvolutional Layers in Classic CNN Processors","authors":"Dawen Xu, Kaijie Tu, Y. Wang, Cheng Liu, Bingsheng He, Huawei Li","doi":"10.1145/3240765.3240810","DOIUrl":"https://doi.org/10.1145/3240765.3240810","url":null,"abstract":"Unlike standard Convolutional Neural Networks (CNNs) with fully-connected layers, Fully Convolutional Neural Networks (FCN) are prevalent in computer vision applications such as object detection, semantic/image segmentation, and the most popular generative tasks based on Generative Adversarial Networks (GAN). In an FCN, traditional convolutional layers and deconvolutional layers contribute to the majority of the computation complexity. However, prior deep learning accelerator designs mostly focus on CNN optimization. They either use independent compute-resources to handle deconvolution or convert deconvolutional layers (Deconv) into general convolution operations, which arouses considerable overhead. To address this problem, we propose a unified fully convolutional accelerator aiming to handle both the deconvolutional and convolutional layers with a single processing element (PE) array. We re-optimize the conventional CNN accelerator architecture of regular 2D processing elements array, to enable it more efficiently support the data flow of deconvolutional layer inference. By exploiting the locality in deconvolutional filters, this architecture reduces the consumption of on-chip memory communication from 24.79 GB to 6.56 GB and improves the power efficiency significantly. Compared to prior baseline deconvolution acceleration scheme, the proposed accelerator achieves 1.3X–44.9X speedup and reduces the energy consumption by 14.60/0-97.6% on a set of representative benchmark applications. Meanwhile, it keeps similar CNN inference performance to that of an optimized CNN-only accelerator with negligible power consumption and chip area overhead.","PeriodicalId":413037,"journal":{"name":"2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124775172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Strain-Aware Performance Evaluation and Correction for OTFT-Based Flexible Displays 基于otft的柔性显示器应变感知性能评估与校正

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2018-11-05 DOI: 10.1145/3240765.3240853

Tengtao Li, S. Sapatnekar

{"title":"Strain-Aware Performance Evaluation and Correction for OTFT-Based Flexible Displays","authors":"Tengtao Li, S. Sapatnekar","doi":"10.1145/3240765.3240853","DOIUrl":"https://doi.org/10.1145/3240765.3240853","url":null,"abstract":"Organic thin-film transistors (OTFTs) are widely used in flexible circuits, such as flexible displays, sensor arrays, and radio frequency identification cards (RFIDs), because these technologies offer features such as better flexibility, lower cost, and easy manufacturability using low-temperature fabrication process. This paper develops a procedure that evaluates the performance of flexible displays. Due to their very nature, flexible displays experience significant mechanical strain/stress in the field due to the deformation caused during daily use. These deformations can impact device and circuit performance, potentially causing a loss in functionality. This paper first models the effects of extrinsic strain due to two fundamental deformations modes, bending and twisting. Next, this strain is translated to variations in device mobility, after which analytical models for error analysis in the flexible display are derived based on the rendered image values in each pixel of the display. Finally, two error correction approaches for flexible displays are proposed, based on voltage compensation and flexible clocking.","PeriodicalId":413037,"journal":{"name":"2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"5 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120967577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1