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2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software最新文献

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On the portability and performance of fully monolithic transformer structures for RF power amplfiers in standard CMOS process 标准CMOS工艺下射频功率放大器全单片变压器结构的可移植性和性能研究
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695929
Jerry Lopez, D. Lie, R. Staszewski, Daquan Huang, C. Hung, Sankaran Swaminathan
{"title":"On the portability and performance of fully monolithic transformer structures for RF power amplfiers in standard CMOS process","authors":"Jerry Lopez, D. Lie, R. Staszewski, Daquan Huang, C. Hung, Sankaran Swaminathan","doi":"10.1109/DCAS.2008.4695929","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695929","url":null,"abstract":"In this paper, we examine several proposed power combining topologies for RF power amplifiers (PA). These structures are simulated in a generic 45 nm CMOS process to allow for comparison of their process portability distinguishing necessary adaptations for reasonable performance. The power combining structures are compared and explored by means of electromagnetic (EM) simulations to help establish an attainable baseline performance using classical transformer structures for fully monolithic combiners with standard CMOS processes.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129673263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A linearized CMOS Quad using selective even feedback 使用选择性均匀反馈的线性化CMOS四轴电路
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695926
V. Acharya, B. Banerjee, T. R. Viswanathan
{"title":"A linearized CMOS Quad using selective even feedback","authors":"V. Acharya, B. Banerjee, T. R. Viswanathan","doi":"10.1109/DCAS.2008.4695926","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695926","url":null,"abstract":"A CMOS Quad containing two asymmetric differential-pairs when driven by a differential input-voltage generates two output-currents: one that is approximately proportional to the input-voltage, and the other, to the square of the input-voltage. We present a simple circuit modification that feeds back the square-law current to linearize the Quad and hence reducing distortion. Also this feedback enables us to take differential output current without demanding high common mode rejection ratio from the next stage. Analytical results based on the simple square-law model for the FETs are presented. Simulation results obtained from large-signal analysis using 0.18 mum TSMC BSIM3 models show that the total harmonic distortion is below 0.25% for a 1 KHz sinusoidal input. Distortion remains low up to a frequency of 1 GHz.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126090429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS differential noise cancelling low noise transconductance amplifier 一种CMOS差分降噪低噪声跨导放大器
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695919
Xi Chen, J. Silva-Martínez, S. Hoyos
{"title":"A CMOS differential noise cancelling low noise transconductance amplifier","authors":"Xi Chen, J. Silva-Martínez, S. Hoyos","doi":"10.1109/DCAS.2008.4695919","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695919","url":null,"abstract":"In this paper a two stage CMOS Radio Frequency (RF) low noise transconductance amplifier is proposed. The feed-forward noise-cancelling technique is exploited to improve the Noise Figure (NF). Simulations with 45 nm CMOS process have been performed to verify the proposed design. The LNA achieves a transconductance of 115 mS, -3 dB bandwidth of 4.5 GHz, NF of 3.4 dB and IIP3 of -10 dBm. Compared to the single stage transconductance amplifier, the in band NF improves by 3.3 dB. The power consumption is 40 mW.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128082304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Developing a fast and inexpensive low power design strategy 开发一种快速、廉价的低功耗设计策略
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695925
Mayank Singh, C. Giacomotto, V. Oklobdzija
{"title":"Developing a fast and inexpensive low power design strategy","authors":"Mayank Singh, C. Giacomotto, V. Oklobdzija","doi":"10.1109/DCAS.2008.4695925","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695925","url":null,"abstract":"A low power circuit design strategy is presented. We believe this methodology can be used to develop fast and inexpensive techniques to aid designers in power optimizations which are generally compute time hungry. The design strategy explored allows for fast sizing of the circuit to get to within 5% of an optimal operating point in terms of energy. Traditional optimization for energy uses time consuming, exhaustive simulations to determine the best possible operating point. The design rules being developed aim to predict the energy optimal point with accuracy but more importantly assist designers to arrive at a minimum energy solution quickly and explore design options better. Furthermore these rules can be used to develop optimization tools which are several orders of magnitude faster than current linear programming and convex optimization tools.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122454760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interference cancellation in receivers with interference frequency estimation 基于干扰频率估计的接收机干扰消除
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695918
C. Sun, S. Ayazian, Xin Wang, R. Gharpurey
{"title":"Interference cancellation in receivers with interference frequency estimation","authors":"C. Sun, S. Ayazian, Xin Wang, R. Gharpurey","doi":"10.1109/DCAS.2008.4695918","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695918","url":null,"abstract":"An interference cancellation technique is described for improving the dynamic range of receivers. Feed-forward cancellation is employed to attenuate interferers by extracting interferers in a parallel auxiliary receiver path, and subtracting these at the output of the LNA, so that the linearity requirement of the down-conversion mixer within the main path of the receiver can be relaxed. The auxiliary path in this implementation needs an estimate of the center frequency of the interferer, which may be modulated in general. A PLL-based technique is employed for this purpose. Measurement results of a prototype implementation are used to validate the approach.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129171339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6-bit 300-MS/s 2.7mW ADC based on linear voltage controlled delay line 基于线性压控延迟线的6位300 ms /s 2.7mW ADC
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695930
Chaoming Zhang, J. Abraham, A. Hassibi
{"title":"A 6-bit 300-MS/s 2.7mW ADC based on linear voltage controlled delay line","authors":"Chaoming Zhang, J. Abraham, A. Hassibi","doi":"10.1109/DCAS.2008.4695930","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695930","url":null,"abstract":"This paper describes a novel ADC architecture based on time domain processing. By using a voltage controlled delay line, a linear transfer function of the input dependent delay is formed. The time delay difference is then compared to a reference to generate a digital code for the input. We have designed a 300-MS/s 6 bit ADC using this architecture in a 0.13 m standard digital CMOS. The simulation results show 36.6 dB SNR, 34.1 dB SNDR for 99 MHz input, DNL<0.2LSB, and INL<0.5LSB. Overall chip power is 2.7 mW with a 1.2 V power supply.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"474 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126391631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Automatic generation of random stimuli sources based on Parameter Domains for functional verification 基于参数域的随机刺激源自动生成功能验证
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695923
C. I. Castro, E. Romero, M. Strum, W. Chau
{"title":"Automatic generation of random stimuli sources based on Parameter Domains for functional verification","authors":"C. I. Castro, E. Romero, M. Strum, W. Chau","doi":"10.1109/DCAS.2008.4695923","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695923","url":null,"abstract":"Functional verification is based on the simulation of a circuitpsilas hardware design language (HDL) model at register transfer level (RTL) and checking the results against the specification. Random stimuli generation has been largely used in different testbench architectures, but the manual coding of the stimuli sources may lead to the stimulation of redundant and invalid test vectors what causes a negative impact on verification performance. They can be eliminated by taking advantage of the dependencies of designpsilas input parameters, splitting the simulation space into parameter domains. In this paper we propose an efficient functional verification methodology based on the parameter domains framework and constraint based random stimulation. Additionally, the paper presents a tool to automatically generate SystemC stimuli sources from modulepsilas parameter domains specification, providing an extra verification time save-up.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126096273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The dynamic stability of a 10T SRAM compared to 6T SRAMs at the 32nm node using an accelerated Monte Carlo technique 采用加速蒙特卡罗技术比较10T SRAM与6T SRAM在32nm节点的动态稳定性
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695924
A. Seshadri, T. Houston
{"title":"The dynamic stability of a 10T SRAM compared to 6T SRAMs at the 32nm node using an accelerated Monte Carlo technique","authors":"A. Seshadri, T. Houston","doi":"10.1109/DCAS.2008.4695924","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695924","url":null,"abstract":"An accelerated Monte Carlo technique is proposed to analyze the dynamic stability margin of SRAM cells. This technique greatly improves accuracy of the desired failure probabilities by, not approximating or making assumptions of fail tail distributions, enhancing fail rate with acceleration, while reducing computations by several orders of magnitude. An application comparing three 6 T SRAM cells and a novel 10 T SRAM cell at the 32 nm node is discussed.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125865835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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