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2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software最新文献

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An accurate gate delay model for high speed digital and analog circuits 一种适用于高速数字和模拟电路的精确门延迟模型
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695915
J. Dobes, V. Panko, L. Pospisil
{"title":"An accurate gate delay model for high speed digital and analog circuits","authors":"J. Dobes, V. Panko, L. Pospisil","doi":"10.1109/DCAS.2008.4695915","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695915","url":null,"abstract":"At present, most of simulation programs can characterize gate delays of microwave transistors. However, the delay is mostly approximated by means of a first-order differential equation only. In the paper, a more accurate way is suggested which is based on an appropriate second-order Bessel function. The delay model is implemented to a slightly but efficiently modified classic MESFET model. The proposed model does not create spurious oscillations that are typical for any LC approximations, and the simulation times are comparable with those obtained without the delay model. Properties of the implementation of the second-order Bessel function are demonstrated by an analysis of a tunable distributed microwave oscillator.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116409439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Two zero and two pole active compensation replaces a charge pump in PLLs 两个零和两极有源补偿取代了锁相环中的电荷泵
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695914
S. Goldman
{"title":"Two zero and two pole active compensation replaces a charge pump in PLLs","authors":"S. Goldman","doi":"10.1109/DCAS.2008.4695914","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695914","url":null,"abstract":"A 2 zero and 2 pole compensation circuit with an operational amplifier replacing a charge pump in a PLL has been fabricated in an 0.065 mum gate length CMOS technology. It achieves state of art performance with 1 mW low power dissipation at 240 MHz output frequency and a small 0.06 mm2 area. The circuit has a wide output frequency range of 12-600 MHz with a low jitter measurement of 80 ps peak to peak.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134014800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A limited bandwidth envelope follower for efficiency enhancement in a linear Power Amplifier in broadband transmitters 用于提高宽带发射机线性功率放大器效率的有限带宽包络从动器
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695920
S. Modi, S. Kanigere, O. Eliezer, P. Balsara
{"title":"A limited bandwidth envelope follower for efficiency enhancement in a linear Power Amplifier in broadband transmitters","authors":"S. Modi, S. Kanigere, O. Eliezer, P. Balsara","doi":"10.1109/DCAS.2008.4695920","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695920","url":null,"abstract":"An efficiency enhancement scheme for transmitters using a linear power amplifier (PA) for nonconstant amplitude modulation is proposed. Various current and emerging wireless standards require envelope modulation with wide bandwidth. It is difficult to accommodate this in PA supply-modulation schemes using an efficient switched regulator (or S-modulator) to follow the envelope signal, as the regulation efficiency declines with the increase in bandwidth. In the proposed scheme a linear PA is used, having a switched power supply that is modulated with a limited bandwidth, while an amplitude modulated signal, which may be predistorted, is fed to the PA input. The presented real-time signal processing algorithm generates a limited bandwidth power supply modulation signal to minimize the average headroom in the PA, thus increasing its efficiency, while also allowing the switched-regulator to retain high modulation efficiency. Implementation area and power consumption are estimated for 0.18 mum CMOS.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123412703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Envelope and phase path recombination in ADPLL-based wideband polar transmitters 基于adpll的宽带极化发射机的包络和相路复合
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695931
I. Syllaios, P. Balsara, R. Staszewski
{"title":"Envelope and phase path recombination in ADPLL-based wideband polar transmitters","authors":"I. Syllaios, P. Balsara, R. Staszewski","doi":"10.1109/DCAS.2008.4695931","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695931","url":null,"abstract":"We investigate the recombination of the RF envelope and phase/frequency paths in a polar transmitter, which is based here on an all-digital phase-locked loop (ADPLL) with a wideband modulation capability. Direct phase/frequency modulation of the digitally-controlled oscillator (DCO) is achieved by means of a two-point modulation scheme of the ADPLL. This scheme views the ADPLL as an all-pass digital filter for the discrete-time baseband phase samples but a low-pass reconstruction filter in the continuous-time domain of the RF DCO output. It is shown analytically that the DCO gain estimation highly affects the interpolative behavior of the ADPLL, which under exact gain estimation, is equivalent to a linear interpolator with sinc2(f)-type transfer function. Given this low-pass behavior of the ADPLL, simple quantitative analysis indicates that optimum phase and RF envelope recombination is achieved when the digital baseband envelope is reconstructed with a filter that closely approximates the ADPLL interpolative transfer function. Furthermore, the cumulative low-pass behavior of the digital polar transmitter mandates the baseband processing rate of the envelope and, more importantly, the phase, be high enough (on the order of a few hundred MHz) so that the recombined RF spectrum meets the stringent performance requirements of emerging communications standards, such as LTE and WiMAX. Fortunately, the use of envelope and phase pre-distortion counterbalances the need for excessively high baseband processing rates.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121150365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low-IF WiMAX RF transceiver in 0.18μm CMOS technology 采用0.18μm CMOS技术的低中频WiMAX射频收发器
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695927
A. Taparia, Syed Askari Nakvi, B. Banerjee
{"title":"A low-IF WiMAX RF transceiver in 0.18μm CMOS technology","authors":"A. Taparia, Syed Askari Nakvi, B. Banerjee","doi":"10.1109/DCAS.2008.4695927","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695927","url":null,"abstract":"This paper describes a dual band low-IF transceiver front-end for the Mobile WiMAX (802.16e) standard. The transceiver is implemented in TSMC 0.18 mum CMOS technology and covers the frequency ranges from 2.3 - 2.7 GHz. The front end transmitter provides an output gain control of 50 dB with an EVM below 3%, where as the receiver achieves gain of 37 dB and a noise figure of 3.7 dB. The components included in the system are low noise amplifier, Active and passive mixers, voltage controlled oscillator and Class- A power Amplifier.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122644021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Active inductor for power-supply decoupling in mixed signal systems 用于混合信号系统电源去耦的有源电感
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695916
A. Taparia, T. R. Viswanathan, B. Banerjee
{"title":"Active inductor for power-supply decoupling in mixed signal systems","authors":"A. Taparia, T. R. Viswanathan, B. Banerjee","doi":"10.1109/DCAS.2008.4695916","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695916","url":null,"abstract":"A CMOS active inductor circuit intended for power-supply decoupling application is presented. The idea is to minimize the switching noise generated by the digital part of a mixed-signal integrated circuit. This is essential when sensitive analog circuits share the same power supply bus with a digital signal processor. In systems with a single clock, the frequency components of the switching noise are the clock frequency and its harmonics. As clock frequencies exceed 1 GHz, the circuit for filtering the switching noise needs only a modest amount of chip area and thus it can be integrated. Simulation results of the proposed circuit using GSMC 0.18 micron CMOS models are used to arrive at the basis for the design of a decoupling scheme.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116790848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Real-time optimization of Viola -Jones face detection for mobile platforms 实时优化的Viola -Jones面部检测的移动平台
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695921
Jianfeng Ren, Nasser Kehtarnavaz, L. Estevez
{"title":"Real-time optimization of Viola -Jones face detection for mobile platforms","authors":"Jianfeng Ren, Nasser Kehtarnavaz, L. Estevez","doi":"10.1109/DCAS.2008.4695921","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695921","url":null,"abstract":"Face detection algorithms based on the Viola-Jones object detection approach is widely adopted in digital camera products. Due to the computational complexity of these algorithms, often a hardware coprocessor is used for their real-time operation. This paper discusses how to achieve real-time software-based implementation of these algorithms on mobile devices that have relatively limited processing and memory capabilities. Various optimization techniques are discussed and an example implementation outcome on an actual mobile platform is presented.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131333257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Accuracy and repeatability of noise measurements with a discrete Fourier transform 用离散傅立叶变换测量噪声的准确性和可重复性
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695922
Ross A. Kulak
{"title":"Accuracy and repeatability of noise measurements with a discrete Fourier transform","authors":"Ross A. Kulak","doi":"10.1109/DCAS.2008.4695922","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695922","url":null,"abstract":"Noise and signal-to-noise measurements are often made using sampled signals and discrete Fourier transforms. In addition to the sampling and circular spectrum issues associated with making an accurate measurement, it is important to understand how accurate and repeatable the measurement is. This work provides an analysis of the expected accuracy of a spectral noise measurement and a method to determine the accuracy for a generic measurement system. Simulation results and experimental data are provided to support the analysis.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124553866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Bottom up approach to enhance top level SoC verification 自底向上的方法来加强顶层SoC验证
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695928
G. Lakshmanan, S. Dhamankar, S. Tare, V. Sharma
{"title":"Bottom up approach to enhance top level SoC verification","authors":"G. Lakshmanan, S. Dhamankar, S. Tare, V. Sharma","doi":"10.1109/DCAS.2008.4695928","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695928","url":null,"abstract":"SoCs today rely heavily on behavioral models of analog circuits for Top Level Verification. The minimum modeling requirement is to model the functional behavior of the circuit. A lot of ongoing work is also focused on modeling analog circuits to predict the system performance of the SoC. This paper presents a methodology to enhance the quality of SoC verification by using a bottom up approach to verify the equivalence of building blocks and then work at higher levels to increase coverage. It is shown that this methodology can be used to verify functional and performance equivalence of behavioral models.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115490532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A highly integrated GPS front-end for cellular applications in 90nm CMOS 高度集成的GPS前端，用于90纳米CMOS的蜂窝应用
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software Pub Date : 2008-12-08 DOI: 10.1109/DCAS.2008.4695917
N. Yanduru, K. Low
{"title":"A highly integrated GPS front-end for cellular applications in 90nm CMOS","authors":"N. Yanduru, K. Low","doi":"10.1109/DCAS.2008.4695917","DOIUrl":"https://doi.org/10.1109/DCAS.2008.4695917","url":null,"abstract":"A GPS receiver front-end consisting of an LNA and a mixer implemented in a 90 nm CMOS process is presented. The measured performance satisfies the linearity requirement set by cellular blockers, without requiring an external LNA or SAW filter that are typically used in GPS receivers for cellular applications. A highly linear RF mixer is designed for this purpose that exploits the short channel effect of deep sub-micron CMOS. The LNA has a single-ended input and provides a differential output. The front-end achieves 38 dB of voltage gain and a noise figure of 1.8 dB. The IIP3 performance is a function of the offset between the GPS signal and the two-tone interferers and varies from -6 dBm to 15 dBm. The NF degradation in the presence of a -30 dBm DCS band blocker is less than 0.5 dB.","PeriodicalId":412051,"journal":{"name":"2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124969880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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