ACM-SE 28最新文献

{"title":"GSPM models: sensitivity analysis and applications","authors":"J. Muppala, Kishor S. Trivedi","doi":"10.1145/98949.98962","DOIUrl":"https://doi.org/10.1145/98949.98962","url":null,"abstract":"Sensitivity analysis of continuous time Markov chains has been considered recently by several re­ searchers. This is very useful in performing bottle­ neck analysis and optimization on systems especially during the design stage. However the construction of these large and complex Markov models is tedious and error-prone process. Generalized Stochastic Petri Nets (GSPN) provide a very useful high-level inter­ face for the automatic generation of the underlying Markov chain. This paper extends parametric sensi­ tivity analysis to GSPN models. The rates and proba­ bilities of the transitions of GSPN models are defined as functions of an independent variable. Equations for the sensitivity analysis of steady-state and transient measures of GSPN and GSPN reward models are de­ veloped and implemented in a software package. An example illustrating the use of sensitivity analysis is presented.","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121074083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multiprocessor computer system for distributing real-time Ada applications","authors":"G. Croucher","doi":"10.1145/98949.99076","DOIUrl":"https://doi.org/10.1145/98949.99076","url":null,"abstract":"Real-Time Ada applications typically used to drive monitors, simulators, and training facilities are becoming increasingly more complex. The designs of these applications are often too complex to be confined to a single problem domain. One possible solution is to provide a target computer system and environment capable of distributing these large-scale Ada applications over multiple processors for parallel execution. The Ada Real-Time Executive (ARTE) and parallel Ada compiler projects currently under development at Encore Computer Corporation are efforts to produce the type of target environment capable of executing these complex applications at an acceptable rate of speed. Major design considerations for this real-time target environment are threefold. First, system hardware must be designed so that it provides maximum processor throughput while minimizing memory and bus contention between processors. Second, the system software used to distribute the application must utilize the processors in an efficient and timely fashion. Finally, the developer's needs must be considered when providing functional (runtime) support visible to the target application. Hardware configurations, ranging from a configuration of very tightly coupled processors sharing a single local memory (see figure 1) to a tightly coupled configuration of processors with individual local memories and a range of shared memory (sec figure 2), arc considered. Fig. 1. Avery tightly coupled system where processors contend for local memory. Permission to copy without fee all or pari of this material is granted provided that the copies are not made or distributed for direct com­ mercial advantage, (lie ACM copyright notice and (lie title of the publication and its date appear, and notice Is given (hat copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific per­ mission. A very tightly coupled processor configuration is generally more acceptable since all processors hnvc visibility to all of memory. A tightly coupled processor architecture is useful in cases where memory or bus contention have become a bottleneck and need to be reduced. < Local (private) memory area jlobal (optional) memory system s memory area r *-* Processor N Local (private) memory area Normal memory systems ~ * Dual ported __ lobal (optional) memory area Processor write operations Into the global memory areas _arc copied onto the RMS h n s^ and get written In the memor les of all nodes on the bus Reflective Memory System Bus Fig. 2. A tightly coupled system where …","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123089567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On the maximum stable set of a permutation graph","authors":"Haklin Kim","doi":"10.1145/98949.99111","DOIUrl":"https://doi.org/10.1145/98949.99111","url":null,"abstract":". . . . 7r j[ is the position in the sequence where the number i can be found [3]. Any vertex adjacent to vertex i is said to be dominated by i while any other vertex is independent(stable) of i. A subset of the vertices of a graph G = (V,E) is a stable set if no two vertices in the subset are adjacent. A stable set is maximal if any vertex not in the set is dominated by at least one vertex in it. 1(G) is the cardinality of maximum stable set. Permutation graphs were introduced by Even and Pnnueli in 1971 [4]. They also showed the transitivity of permutation graphs and an 0(n2) algorithm to find a maximum stable set [1]. In [3] Golumbic showed an 0(n log n) algorithm to find the chromatic number C(G). The domination problems in permutation graphs were studied by Farber and Keil [2]. They presented an 0(n2) algorithm to find a minimum dominating set.","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"495 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134436661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The FHDL ROM tools","authors":"P. Maurer, C. D. Morency","doi":"10.1145/98949.98960","DOIUrl":"https://doi.org/10.1145/98949.98960","url":null,"abstract":"The FHDL (Florida Hardware Design Language) ROM tools provide a method for specifying, simulating, and automatically laying out ROMs. The primary focus of the ROM tools is on providing powerful methods for specifying microcode. Because the ROM tools were designed to support both VLSI design projects and other course work in hardware design, the ROM language contains many features that allow it to emulate other ROM programming languages. This allows students to complete laboratory exercises using a language that is similar to the one used in their textbook. Once the contents of a ROM have been specified, the ROM can be simulated concurrently with the simulation of the other hardware comprising the design. This allows designs to be debugged before they are fabricated. Once a design has been verified, the ROM can be laid out automatically and incorporated into a larger VLSI circuit. The automatic layout portion of the FHDL ROM tools is the subject of on-going research at the University of South Florida.","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134522113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A knowledge-based approach to real-time systems","authors":"R. Ghaly, N. Prabhakaran","doi":"10.1145/98949.99096","DOIUrl":"https://doi.org/10.1145/98949.99096","url":null,"abstract":"We select the OSAM* model for the knowledge base representation [2] and extend it with real time aspects.The reason for our selection of OSAM* is that it has versatile semantic associa­ tion types that increase the functionality of the system. OSAM* supports generalization, aggregation, interaction, cross product composition associations and follows the object oriented paradigm. It supports encapsulation and multiple inheritance mechanisms. The association types con­ trol the visibility among different entities of the application domain. OSAM* class definition integrates not only the structural and behavioral properties of similar objects, but also specifies the knowledge rule among those properties. The rule base is an integral part of the system and is homogeneously designed and is integrated with object classes. Real time aspects require the management of the critical situations that may arise in application domains within the specified time limit. Recently, real time systems deal with very large amount of data that require a more intelligent kernel to allow reasoning about application domain rules. Among other related works is the HiPAC project [1], that attempts to deal with timing constraints, and proposes contingency plans. POSTGRES provides alerters and triggers with which forward and backward reasoning mechanism can be realized. SYBASE supports situation action rules on database operations with restricted conditions and actions. Permission lo copy willioul fee all or pail of lliis material is granted provided that die copies are not made or distributed for direct com­ mercial advantage, die ACM copyright notice and the title of Hie publication and its dale appear, and notice Is given that copying Is by permission of the Association for Computing Machinery. To copy olltenvise, or to republish, requires a fee and/or specific per­ mission. Our work will be the embedding of real time aspects into the rules and operations of each class. The timing constraints to an operation are more specific than to a class. A crucial problem in real time systems is the execution of an urgent request while another less urgent request is running. The resolution of these conflicts is the basis for most scheduling algorithms that are designed to deal with a more intelligent real time system. This rule base design is built on some basic definitions, such as event, priority and hard-deadline. These properties of class rules as well as operation rules are inherited by subclassesOur algorithm computes a dynamic weighted priority for each re­ quest by taking into account the criticalness of the request, time needed for the completion of the request, and the time left for the re­ quest. Then the request with the highest dynamic priority takes precedence over others. The uniform representation of rules as classes in the design of the knowledge base as­ sists in removing redundancy and improving the efficiency of the KBMS design.","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131108423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards the implementation of intelligent structures in intensive care monitoring: the advantages of the symbolic pre-processing","authors":"V. Moret-Bonillo, Amparo Alonso-Betanzos, J. Searle","doi":"10.1145/98949.99125","DOIUrl":"https://doi.org/10.1145/98949.99125","url":null,"abstract":"V ic e n te M o rc t-B o n lllo , A m p a ro A lo n soB c ta n z o s, J o h n R. S c a rle A b s tr a c t Intensive care of patients requires the management of a large quantity of Information which must be Interpreted differently for each specific case. Until now. efforts to improve the quality of monitoring systems have followed two different approaches a)nuildlng sophisticated acquisition and storage equipment allowing friendly presentation of the results, and b) Building expert systems. In tills paper we propose an alternative approach that combines deterministic and heuristic techniques. The core of the approach consists of performing the symbolic processing of the numerical data before running the inferential structure of the overall system. I n tr o d u c t io n In th e ICU e n v ir o n m e n t th e h e te ro g e n e ity o f th e p a t ie n t s is th e d o m i n a n t p a tte r n , a n d th e c r ite r ia for in t e r p r e ta tio n o f th e re s p e c tiv e m o n ito r e d p a r a m e ­ te r s v a ry d e p e n d in g o n th e o rig in a l c a u s e s t h a t m o ti­ v a te d th e ir a d m is s io n in th e U n it. C e r ta in c h a r a c t e r i s ­ tic s I n h e r e n t to e a c h p a t ie n t m a y m o d ify th e c r ite r ia for th e in t e r p r e ta t io n o f th e c o r r e s p o n d in g m e a s u r e m e n ts [1]. B u ild in g …","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":" 44","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132159418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimizing the design of a hydrostatic thrust bearing by applying genetic algorithms","authors":"Koushik Banerjee","doi":"10.1145/98949.99152","DOIUrl":"https://doi.org/10.1145/98949.99152","url":null,"abstract":"This paper considers optimizing the design of a hydro­ static thrust bearing by applying genetic algorithms ((7,4s). This is a practical design problem, and the ob­ jective is (i) to confirm that GAs can be successfully applied as an optimization tool in complex engineering design problems,and (it) that the mutation operator in a simple GA can serve as an extremely powerful tool in locating the global optima in the search space in a complicated optimization problem. The optimization criterion involves minimizing the to­ tal power loss to the bearing (U), which is the sum of the pumping energy (Ep) and the frictional loss (Ey). The problem has three design variables and four con­ straints, thus making it a complex optimization prob­ lem irrespective of the optimizing algorithm employed. The problem was earlier solved by the random search technique (rst). GAs are search algorithms based on the mechanics of natural selection and natural genet­ ics. For information on GAs readers are requested to refer [l]. The objective function to be optimized is given by U = E y + E p (1)","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133112660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Identifying students who may experience difficulty in an introductory computer science course","authors":"Ted W. Goodman","doi":"10.1145/98949.98988","DOIUrl":"https://doi.org/10.1145/98949.98988","url":null,"abstract":"A high percentage of the students in introductory computer science (CS1) courses either drop out or fail to perform at an acceptable level. In past years when students were flocking to computer science, student failure rales were not viewed as a problem. Now that student interest in computer science has declined significantly, departments are faced with the problem of how to increase retention rates without compromising the quality of the course. This can be partially accomplished by identifying those students who may experience difficulty and then closely monitoring and assisting these students. This study is concerned with the question: Is it possible to develop a simple and reasonably effective procedure for identifying those students who may experience difficulty in the CS1 course? Prior studies have attempted to predict success In CS1 courses with mixed results. Of these studies, the one most closely related to the present study was conducted by Fowler and Glorefeld [4]. In this study, college GPA, number of math courses, SAT math score, and age were used to develop a model which correctly classified 81 per cent of the students in CS1 courses into two categories, those who received a grade of A or B, and those who received a grade of C, D, or F. Thirty students from two sections of a CS1 course using Pascal at a comprehensive university participated in the present study during the 1988 Fall semester. The final grade was used as a measure of success in the course and was used to classify the students into two groups according to the degree of difficulty that they experienced in the course. Those who received a final grade of Cor lower were placed in a \"high difficulty\" group while those who received a final grade of C or higher were placed in a \"low difficulty\" group. The predictors consisted of classification (CLASS), reason for taking the course (UHY), and four tests covering mathematics background (MATH), logical","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"393 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116017175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compromises and complexities associated with removal of MIS from the logical access authorization loop","authors":"Harlan D. Webre","doi":"10.1145/98949.99031","DOIUrl":"https://doi.org/10.1145/98949.99031","url":null,"abstract":"Logical access to computer-housed assets involves the allowance or denial of access requests to entities such as files, database tables, and programs. Although specific control objectives may vary from site to site in the commercial sector, some basic access control objec­ tives can be identified which are nearly universal. These objectives are based strongly upon the notions of asset ownership and authorization. Control of access to computer-housed assets typicnlly follows the same authorization path as the delegation of control of other types of assets, that is, from the board of directors down to some appropriate, workable level. In many installations, however, the responsibility for granting and revoking access to these entities has tra­ ditionally fallen upon the MIS Data Security Officer. This means that either 1) the Security Officer must gain authorization from the proper authority each time an ac­ cess rule is changed, or 2) the Security Officer is the authority for all assets in his or her domain. Neither one of these is a healthy situation. After development of some general access control objectives and an explanation of why the MIS Data Se­ curity Officer bears the mantle of authority, this paper examines the possibility of placing the mechanics of logical access authorization in the hands of the true authority within the appropriate business function. There are two primary obstacles to achieving this end. One is the sheer magnitude of the number of assets under consideration. In an envimoment in which appli­ cations are built and delivered to automate business ac­ tivities, a single application can contain a very large number of assets. The other obstacle is that of identifica­ tion of assets. Often the naming conventions developed and used by the MIS staff have a great deal of meaning to those who are familiar with the workings of the appli­ cation, but will mean little or nothing to someone out­ side MIS. This paper proposes a method of overcoming these obstacles, but the proposal carries with it a substantial price tag. Compromises must be made in the way that com­ puter resources are used and applications are delivered, and a level of complexity is introduced to the access control system which will most probably strain the secu­ rity features available in the target operating system past the limits of their flexibility. The proposal defines an access package, which represents all the operations and atomic accesses neces­ sary to accomplish a particular business activity. The ac­ cess package can be thought of as an access operation raised to a higher level of abstraction. It allows the asset owner to have a business oriented understanding of Ills or her responsibility. However, if a system of access control based on ac­ cess packages can be engineered, it will require that computer users be limited to executing only those access packages to which they have been given access. This is not an attractive thought as the age of end-use","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116365255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The FHDL macro processor","authors":"P. Maurer","doi":"10.1145/98949.98958","DOIUrl":"https://doi.org/10.1145/98949.98958","url":null,"abstract":"The FHDL (Florida Hardware Design Language) Macro processor provides a mechanism for extending the language features provided by the other components of the FHDL system (the ROM language, the PLA language, and the logic specification language). The primary use of the Macro processor is to provide flexible cells, such as ripple-carry adders, that can expand to match the size of the interface. The use of the Macro processor for this purpose is transparent with more standard hierarchical specification mechanisms. In addition, the Macro processor was designed to be an implementation vehicle for more sophisticated hardware specification and synthesis systems. The Macro processor provides most of the features found in other macro languages, and provides several new features that are found in few, if any, existing macro languages. The use of the Macro processor for high-level synthesis is the subject of much on-going research. THE FHDL MACRO PROCESSOR Peter M. Maurer Department of Computer Science and Engineering University of South Florida Tampa, FL 33620","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128685511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}