Multiprocessor computer system for distributing real-time Ada applications

Real-Time Ada applications typically used to drive monitors, simulators, and training facilities are becoming increasingly more complex. The designs of these applications are often too complex to be confined to a single problem domain. One possible solution is to provide a target computer system and environment capable of distributing these large-scale Ada applications over multiple processors for parallel execution. The Ada Real-Time Executive (ARTE) and parallel Ada compiler projects currently under development at Encore Computer Corporation are efforts to produce the type of target environment capable of executing these complex applications at an acceptable rate of speed. Major design considerations for this real-time target environment are threefold. First, system hardware must be designed so that it provides maximum processor throughput while minimizing memory and bus contention between processors. Second, the system software used to distribute the application must utilize the processors in an efficient and timely fashion. Finally, the developer's needs must be considered when providing functional (runtime) support visible to the target application. Hardware configurations, ranging from a configuration of very tightly coupled processors sharing a single local memory (see figure 1) to a tightly coupled configuration of processors with individual local memories and a range of shared memory (sec figure 2), arc considered. Fig. 1. Avery tightly coupled system where processors contend for local memory. Permission to copy without fee all or pari of this material is granted provided that the copies are not made or distributed for direct com­ mercial advantage, (lie ACM copyright notice and (lie title of the publication and its date appear, and notice Is given (hat copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific per­ mission. A very tightly coupled processor configuration is generally more acceptable since all processors hnvc visibility to all of memory. A tightly coupled processor architecture is useful in cases where memory or bus contention have become a bottleneck and need to be reduced. < Local (private) memory area jlobal (optional) memory system s memory area r *-* Processor N Local (private) memory area Normal memory systems ~ * Dual ported __ lobal (optional) memory area Processor write operations Into the global memory areas _arc copied onto the RMS h n s^ and get written In the memor les of all nodes on the bus Reflective Memory System Bus Fig. 2. A tightly coupled system where …