2012 25th International Conference on VLSI Design最新文献_第5页

Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation 序列电路中可达敏感路径的SAT和Craig插值分析

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.101

M. Sauer, Stefan Kupferschmid, A. Czutro, S. Reddy, B. Becker

引用次数: 6

An Energy Efficient Oscillator Frequency Calibration Methodology Using Fraction Phase Computation 一种基于分数相位计算的节能振荡器频率校准方法

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.51

Amitava Ghosh, Isha Das, Achintya Halder

引用次数: 2

A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection 针对更好的故障检测的测试集选择的可诊断性度量

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.110

Subhadip Kundu, S. Chattopadhyay, I. Sengupta, R. Kapur

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引用次数: 2

Embedded Tutorial ET3: Packaging Trends, Die Package Co-Design Flow and Challenges 嵌入式教程ET3:封装趋势，模具封装协同设计流程和挑战

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.40

Siva Kothamasu

引用次数: 0

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip 用于48ia -32核心片上网络的45nm CMOS可重构片上流量发生器

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.86

Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Y. Hoskote, Satish Yada, Shasi Kumar, V. Erraguntla, S. Vangal, N. Borkar

{"title":"A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip","authors":"Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Y. Hoskote, Satish Yada, Shasi Kumar, V. Erraguntla, S. Vangal, N. Borkar","doi":"10.1109/VLSID.2012.86","DOIUrl":"https://doi.org/10.1109/VLSID.2012.86","url":null,"abstract":"A reconfigurable on-die Traffic Generator (TG) is proposed to test the packet switched 2D-mesh network of a 48 iA-32 core Single-chip Cloud Computer. The Single-chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. The 24-tile Network-on-Chip (NoC) consists of a Traffic Generator per tile which can be programmed to generate deterministic and random traffic patterns. It also consists of reconfigurable activity control, (non)-cacheable reads and writes, message class and route control bits to feed synthetic traffic to the network to investigate NoC functional, protocol issues and to measure the key power-performance metrics. In this paper, we present the architecture and design details of the Traffic Generator, operating modes, re-configurability and the testing procedures. This semi-custom design has a transistor count of 54K, which is 0.1% of tile transistor count, and occupies 0.3mm2 area which is 0.9% of tile area. The estimated power consumption is only 23mW at 1.1V and at 500C, 0.02% of the total chip power in 45nm high-K nine metal CMOS process.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123205528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias 基于核的3D硅通孔堆叠集成电路的测试规划

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.111

B. SenGupta, Urban Ingelsson, E. Larsson

引用次数: 3

An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs 低功耗sram的面积高效二极管和晶体管可互换电源门控方案与微调选项

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.50

A. Goel, D. Evans, Richard Stephani, V. Reddy, Dharmendra Rai, V. Chary, N. Sathisha

引用次数: 2

A Novel SMT-Based Technique for LFSR Reseeding 一种基于smt的LFSR重播新技术

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.103

S. Prabhu, M. Hsiao, L. Lingappan, V. Gangaram

引用次数: 8

Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management 具有宽电压范围的双向单电源电平移位器，用于高效电源管理

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.58

S. Manohar, V. Somasundar, R. Venkatasubramanian, P. Balsara

引用次数: 8

Analysis of the Pull-In Phenomenon in Microelectromechanical Varactors 微机电变容管中的拉入现象分析

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.68

A. Roy, A. Bhattacharya, R. Chaudhuri, T. K. Bhattacharyya

引用次数: 11