Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems最新文献_第5页

Session details: Session 3A: Memory and Security II 会议详情:会议3A:内存和安全II

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2015-03-14 DOI: 10.1145/3251030

Dan Tsafrir

引用次数: 0

Kinetic Dependence Graphs 动力学依赖图

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2015-03-14 DOI: 10.1145/2694344.2694363

M. A. Hassaan, Donald Nguyen, K. Pingali

{"title":"Kinetic Dependence Graphs","authors":"M. A. Hassaan, Donald Nguyen, K. Pingali","doi":"10.1145/2694344.2694363","DOIUrl":"https://doi.org/10.1145/2694344.2694363","url":null,"abstract":"Task graphs or dependence graphs are used in runtime systems to schedule tasks for parallel execution. In problem domains such as dense linear algebra and signal processing, dependence graphs can be generated from a program by static analysis. However, in emerging problem domains such as graph analytics, the set of tasks and dependences between tasks in a program are complex functions of runtime values and cannot be determined statically. In this paper, we introduce a novel approach for exploiting parallelism in such programs. This approach is based on a data structure called the kinetic dependence graph (KDG), which consists of a dependence graph together with update rules that incrementally update the graph to reflect changes in the dependence structure whenever a task is completed. We have implemented a simple programming model that allows programmers to write these applications at a high level of abstraction, and a runtime within the Galois system [15] that builds the KDG automatically and executes the program in parallel. On a suite of programs that are difficult to parallelize otherwise, we have obtained speedups of up to 33 on 40 cores, out-performing third-party implementations in many cases.","PeriodicalId":403247,"journal":{"name":"Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126788959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Session details: Session 1B: Memory Models I 会话细节:会话1B:内存模型

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2015-03-14 DOI: 10.1145/3251027

A. Lebeck

引用次数: 0

Session details: Keynote II: Keynote Address II 会议详情:主题演讲二:主题演讲二

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2015-03-14 DOI: 10.1145/3251039

K. Ebcioglu

引用次数: 0

DEUCE: Write-Efficient Encryption for Non-Volatile Memories DEUCE:非易失性存储器的写效率加密

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2015-03-14 DOI: 10.1145/2694344.2694387

Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi

{"title":"DEUCE: Write-Efficient Encryption for Non-Volatile Memories","authors":"Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi","doi":"10.1145/2694344.2694387","DOIUrl":"https://doi.org/10.1145/2694344.2694387","url":null,"abstract":"Phase Change Memory (PCM) is an emerging Non Volatile Memory (NVM) technology that has the potential to provide scalable high-density memory systems. While the non-volatility of PCM is a desirable property in order to save leakage power, it also has the undesirable effect of making PCM main memories susceptible to newer modes of security vulnerabilities, for example, accessibility to sensitive data if a PCM DIMM gets stolen. PCM memories can be made secure by encrypting the data. Unfortunately, such encryption comes with a significant overhead in terms of bits written to PCM memory, causing half of the bits in the line to change on every write, even if the actual number of bits being written to memory is small. Our studies show that a typical writeback modifies, on average, only 12% of the bits in the cacheline. Thus, encryption causes almost a 4x increase in the number of bits written to PCM memories. Such extraneous bit writes cause significant increase in write power, reduction in write endurance, and reduction in write bandwidth. To provide the benefit of secure memory in a write efficient manner this paper proposes Dual Counter Encryption (DEUCE). DEUCE is based on the observation that a typical writeback only changes a few words, so DEUCE reencrypts only the words that have changed. We show that DEUCE reduces the number of modified bits per writeback for a secure memory from 50% to 24%, which improves performance by 27% and increases lifetime by 2x.","PeriodicalId":403247,"journal":{"name":"Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123313924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 136

SPECS: A Lightweight Runtime Mechanism for Protecting Software from Security-Critical Processor Bugs SPECS:用于保护软件免受安全关键处理器错误影响的轻量级运行时机制

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2015-03-14 DOI: 10.1145/2694344.2694366

Matthew Hicks, C. Sturton, Samuel T. King, Jonathan M. Smith

引用次数: 56

iThreads: A Threading Library for Parallel Incremental Computation 线程库并行增量计算

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2015-03-14 DOI: 10.1145/2694344.2694371

Pramod Bhatotia, Pedro Fonseca, Umut A. Acar, Björn B. Brandenburg, R. Rodrigues

引用次数: 34

Session details: Session 7A: Memory Models II 会议详情:会议7A:内存模型II

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2015-03-14 DOI: 10.1145/3251040

H. Boehm

引用次数: 0

Session details: Session 4B: Reliability 会话详细信息:会话4B:可靠性

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2015-03-14 DOI: 10.1145/3251033

E. Berger

引用次数: 0

Page Placement Strategies for GPUs within Heterogeneous Memory Systems 异构内存系统中gpu的页面放置策略

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2015-03-14 DOI: 10.1145/2694344.2694381

Neha Agarwal, D. Nellans, M. Stephenson, Mike O'Connor, S. Keckler

{"title":"Page Placement Strategies for GPUs within Heterogeneous Memory Systems","authors":"Neha Agarwal, D. Nellans, M. Stephenson, Mike O'Connor, S. Keckler","doi":"10.1145/2694344.2694381","DOIUrl":"https://doi.org/10.1145/2694344.2694381","url":null,"abstract":"Systems from smartphones to supercomputers are increasingly heterogeneous, being composed of both CPUs and GPUs. To maximize cost and energy efficiency, these systems will increasingly use globally-addressable heterogeneous memory systems, making choices about memory page placement critical to performance. In this work we show that current page placement policies are not sufficient to maximize GPU performance in these heterogeneous memory systems. We propose two new page placement policies that improve GPU performance: one application agnostic and one using application profile information. Our application agnostic policy, bandwidth-aware (BW-AWARE) placement, maximizes GPU throughput by balancing page placement across the memories based on the aggregate memory bandwidth available in a system. Our simulation-based results show that BW-AWARE placement outperforms the existing Linux INTERLEAVE and LOCAL policies by 35% and 18% on average for GPU compute workloads. We build upon BW-AWARE placement by developing a compiler-based profiling mechanism that provides programmers with information about GPU application data structure access patterns. Combining this information with simple program-annotated hints about memory placement, our hint-based page placement approach performs within 90% of oracular page placement on average, largely mitigating the need for costly dynamic page tracking and migration.","PeriodicalId":403247,"journal":{"name":"Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125585910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 133