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1996 Symposium on VLSI Circuits. Digest of Technical Papers最新文献

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Receiver with constant active termination 具有恒定主动终止的接收器
1996 Symposium on VLSI Circuits. Digest of Technical Papers Pub Date : 1996-06-13 DOI: 10.1109/VLSIC.1996.507746
M. Rau, A. Rothermel, H. Pfleiderer
{"title":"Receiver with constant active termination","authors":"M. Rau, A. Rothermel, H. Pfleiderer","doi":"10.1109/VLSIC.1996.507746","DOIUrl":"https://doi.org/10.1109/VLSIC.1996.507746","url":null,"abstract":"The communication link between chips becomes critical in integrated circuit technology. The full swing CMOS signaling is too slow and produces too much /spl Delta/I-noise and crosstalk to sensitive analog parts. Techniques using match-terminated transmission-lines are power consuming or require additional supply voltages. We present a new receiver circuit that allows to transmit digital data fast with extremely small swing and hence low power consumption.","PeriodicalId":399030,"journal":{"name":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","volume":"405 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122899453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A high bandwidth constant g/sub m/ and slew-rate rail-to-rail CMOS amplifier circuit for embedded low-voltage applications 用于嵌入式低压应用的高带宽恒定g/sub /和慢速率轨对轨CMOS放大电路
1996 Symposium on VLSI Circuits. Digest of Technical Papers Pub Date : 1996-06-13 DOI: 10.1109/VLSIC.1996.507750
W. Redman-White
{"title":"A high bandwidth constant g/sub m/ and slew-rate rail-to-rail CMOS amplifier circuit for embedded low-voltage applications","authors":"W. Redman-White","doi":"10.1109/VLSIC.1996.507750","DOIUrl":"https://doi.org/10.1109/VLSIC.1996.507750","url":null,"abstract":"A rail-to-rail CMOS amplifier input structure is presented which maintains near constant g/sub m/ and slew current for any common mode input level. Feedforward is used to achieve high bandwidth, and operation does not depend upon idealised MOS characteristics. The circuit may be used as the input for one or two stage op-amps, transconductors and asynchronous comparators. The near ideal behaviour at any input level means that accurate VHDL modelling is easily performed for large scale integrated system simulation.","PeriodicalId":399030,"journal":{"name":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128771936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Low voltage high speed circuit designs for giga-bit DRAMs 千兆位dram的低电压高速电路设计
1996 Symposium on VLSI Circuits. Digest of Technical Papers Pub Date : 1996-06-13 DOI: 10.1109/VLSIC.1996.507731
K.-C. Lee, C.H. Kim, D. Yoo, J. Sim, S.-B. Lee, B.-S. Moon, K-Y. Kim, N. Kim, Seung-Moon Yoo, Jei-Hwan Yoo, S. Cho
{"title":"Low voltage high speed circuit designs for giga-bit DRAMs","authors":"K.-C. Lee, C.H. Kim, D. Yoo, J. Sim, S.-B. Lee, B.-S. Moon, K-Y. Kim, N. Kim, Seung-Moon Yoo, Jei-Hwan Yoo, S. Cho","doi":"10.1109/VLSIC.1996.507731","DOIUrl":"https://doi.org/10.1109/VLSIC.1996.507731","url":null,"abstract":"An experimental 16 Mb DRAM for giga scale densities with a charge-amplifying boosted sensing (CABS) scheme and a new I/O large gain current sense amplifier using a cross-coupled current mirror control scheme achieves a t/sub RAC/ of 28 ns and an average operating current of 22 mA at V/sub CC/=1.5 V, t/sub RC/=70 ns, T=25/spl deg/C. This chip has been fabricated using a 0.18 /spl mu/m twin-well CMOS process with KrF lithography having transistor channel lengths of 0.32(n)/0.40(p)/spl mu/m and low resistance TiSi/sub 2/ wordlines.","PeriodicalId":399030,"journal":{"name":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132330760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 3 V CMOS video acquisition channel 一个3v CMOS视频采集通道
1996 Symposium on VLSI Circuits. Digest of Technical Papers Pub Date : 1996-06-13 DOI: 10.1109/VLSIC.1996.507729
K. Nakamura, S. Ho, C. Mangelsdorf, K. Nishio
{"title":"A 3 V CMOS video acquisition channel","authors":"K. Nakamura, S. Ho, C. Mangelsdorf, K. Nishio","doi":"10.1109/VLSIC.1996.507729","DOIUrl":"https://doi.org/10.1109/VLSIC.1996.507729","url":null,"abstract":"A complete video acquisition channel has been integrated in a 0.6 /spl mu/m double-poly CMOS process. The system includes a video clamp, AGC, S/H amplifier, and 10-bit ADC. The signal chain is fully differential, and achieves /spl plusmn/0.35 LSB DNL at 14.3 MS/s dissipating 90 mW from a 3 V supply. The active area is 2.85 sq mm.","PeriodicalId":399030,"journal":{"name":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130147877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A modular architecture for a 6.4-Gbyte/s, 8-Mbit media chip 6.4 gb /s, 8mbit媒体芯片的模块化架构
1996 Symposium on VLSI Circuits. Digest of Technical Papers Pub Date : 1996-06-13 DOI: 10.1109/VLSIC.1996.507709
T. Watanabe, R. Fujita, K. Yanagisawa, H. Tanaka, K. Ayukawa, M. Soga, Y. Tanaka, Y. Sugie, Y. Nakagome
{"title":"A modular architecture for a 6.4-Gbyte/s, 8-Mbit media chip","authors":"T. Watanabe, R. Fujita, K. Yanagisawa, H. Tanaka, K. Ayukawa, M. Soga, Y. Tanaka, Y. Sugie, Y. Nakagome","doi":"10.1109/VLSIC.1996.507709","DOIUrl":"https://doi.org/10.1109/VLSIC.1996.507709","url":null,"abstract":"Develops a modular architecture for a DRAM-integrated, multimedia chip, or media chip with a data transfer rate of 6 to 12 Gbyte/s. The DRAM macro enables the design flexibility both for DRAM capacity and the logic-memory interface to meet a wide variety of applications. A 6.4-Gbyte/s. 8-Mbit test chip was fabricated.","PeriodicalId":399030,"journal":{"name":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122359057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An efficient charge recycle and transfer pump circuit for low operating voltage DRAMs 一种用于低工作电压dram的高效电荷回收和传输泵电路
1996 Symposium on VLSI Circuits. Digest of Technical Papers Pub Date : 1996-06-13 DOI: 10.1109/VLSIC.1996.507734
T. Hamamoto, Y. Morooka, T. Amano, H. Ozaki
{"title":"An efficient charge recycle and transfer pump circuit for low operating voltage DRAMs","authors":"T. Hamamoto, Y. Morooka, T. Amano, H. Ozaki","doi":"10.1109/VLSIC.1996.507734","DOIUrl":"https://doi.org/10.1109/VLSIC.1996.507734","url":null,"abstract":"An efficient Vpp generator with a charge recycle pump and a charge transfer pump have been proposed. The charge recycle operation can reduce the Vpp generating current by 38% without decreasing the Vpp supply current. The charge transfer operation enables the generation of the Vpp supply current at over the 2/spl middot/Vcc level. These techniques are highly effective in low voltage DRAMs.","PeriodicalId":399030,"journal":{"name":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128779080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load 深亚v，单电源SRAM单元，具有多v /sub T/，增强存储节点和动态负载
1996 Symposium on VLSI Circuits. Digest of Technical Papers Pub Date : 1996-06-13 DOI: 10.1109/VLSIC.1996.507743
K. Itoh, A. Fridi, A. Bellaouar, M. Elmasry
{"title":"A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load","authors":"K. Itoh, A. Fridi, A. Bellaouar, M. Elmasry","doi":"10.1109/VLSIC.1996.507743","DOIUrl":"https://doi.org/10.1109/VLSIC.1996.507743","url":null,"abstract":"The key issues in ultralow voltage SRAM design are a reduction in power supply voltage to a solar-cell voltage of 0.5V or less, single supply operation, and an increase in the cell voltage-margin. However, these problems remain largely unsolved. Even in most advanced cells an unavoidably high FET threshold voltage (V/sub T/) of the cell compared with the low stored node-voltage of supply restricts the supply to around 1V, although 0.5 V operation has been reported with no cell margin. Moreover, the negative pull down of the cell source line prevents single supply operation, since an on-chip negative voltage generator comprising charge pumping circuits never manages a heavy data-line capacitance. This paper describes an innovative circuit for overcoming these problems, demonstrating the feasibility of a single 0.3 V, 50 MHz, 0.25 /spl mu/m 8Kb SRAM. A multi-V/sub T/ cell, a boosted cell storage-node and a dynamic cell load contribute to the outstanding performance.","PeriodicalId":399030,"journal":{"name":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123280310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 85
A 50% noise reduction interface using low-weight coding 使用低权重编码的50%降噪接口
1996 Symposium on VLSI Circuits. Digest of Technical Papers Pub Date : 1996-06-13 DOI: 10.1109/VLSIC.1996.507748
Kazuyuki Nakamura, Mark A Horowitz
{"title":"A 50% noise reduction interface using low-weight coding","authors":"Kazuyuki Nakamura, Mark A Horowitz","doi":"10.1109/VLSIC.1996.507748","DOIUrl":"https://doi.org/10.1109/VLSIC.1996.507748","url":null,"abstract":"We have experimentally confirmed the theoretically predicted results of -50% noise reduction and -18% power reduction in an LSI interface. With a newly developed analog-MV circuit, delay time in encoding is less than 1-ns (>1 GHz), and layout-area for an 86 to 96 codec is 0.063 mm/sup 2/ in a 0.5 um process. Use of a \"low-weight coding scheme\" with our developed analog-MV circuits appears to be a promising approach to the achievement of GHz-class VLSI interfaces.","PeriodicalId":399030,"journal":{"name":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115291069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
The charge-share modified precharge-level (CSM) architecture for high-speed and low-power ferroelectric memory 高速低功耗铁电存储器的电荷共享改进预电荷级(CSM)结构
1996 Symposium on VLSI Circuits. Digest of Technical Papers Pub Date : 1996-06-13 DOI: 10.1109/VLSIC.1996.507712
H. Fujisawa, T. Sakata, T. Sekiguchi, O. Nagashima, K. Kimura, K. Kajigaya
{"title":"The charge-share modified precharge-level (CSM) architecture for high-speed and low-power ferroelectric memory","authors":"H. Fujisawa, T. Sakata, T. Sekiguchi, O. Nagashima, K. Kimura, K. Kajigaya","doi":"10.1109/VLSIC.1996.507712","DOIUrl":"https://doi.org/10.1109/VLSIC.1996.507712","url":null,"abstract":"We have proposed the charge-share modified precharge-level architecture with self-timing precharge technique. It is a low-power dissipation architecture for achieving high-density, high-speed, and high-operating-margin simultaneously, making it a leading candidate for use in an Mb-scale ferroelectric memory.","PeriodicalId":399030,"journal":{"name":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120998292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAMs 用于千兆DRAM的Vcc/Vss混合预充电的双层位线DRAM阵列
1996 Symposium on VLSI Circuits. Digest of Technical Papers Pub Date : 1996-06-13 DOI: 10.1109/VLSIC.1996.507766
H. Nakano, D. Takashima, K. Tsuchida, S. Shiratake, T. Inaba, M. Ohta, Y. Oowaki, S. Watanabe, K. Ohuchi, J. Matsunaga
{"title":"A dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAMs","authors":"H. Nakano, D. Takashima, K. Tsuchida, S. Shiratake, T. Inaba, M. Ohta, Y. Oowaki, S. Watanabe, K. Ohuchi, J. Matsunaga","doi":"10.1109/VLSIC.1996.507766","DOIUrl":"https://doi.org/10.1109/VLSIC.1996.507766","url":null,"abstract":"A dual layer BL array and a Vcc/Vss hybrid precharge sensing scheme has been proposed. The array affords the maximum memory cell density and relaxed sense amplifier layout which is as wide as the conventional folded BL sense amplifier layout. The Vcc/Vss hybrid precharge scheme gives the doubled operation voltage for sensing compared with the conventional half Vcc precharge method without the BL charge/discharge current increase.","PeriodicalId":399030,"journal":{"name":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123838153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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