Low voltage high speed circuit designs for giga-bit DRAMs

K.-C. Lee, C.H. Kim, D. Yoo, J. Sim, S.-B. Lee, B.-S. Moon, K-Y. Kim, N. Kim, Seung-Moon Yoo, Jei-Hwan Yoo, S. Cho
{"title":"Low voltage high speed circuit designs for giga-bit DRAMs","authors":"K.-C. Lee, C.H. Kim, D. Yoo, J. Sim, S.-B. Lee, B.-S. Moon, K-Y. Kim, N. Kim, Seung-Moon Yoo, Jei-Hwan Yoo, S. Cho","doi":"10.1109/VLSIC.1996.507731","DOIUrl":null,"url":null,"abstract":"An experimental 16 Mb DRAM for giga scale densities with a charge-amplifying boosted sensing (CABS) scheme and a new I/O large gain current sense amplifier using a cross-coupled current mirror control scheme achieves a t/sub RAC/ of 28 ns and an average operating current of 22 mA at V/sub CC/=1.5 V, t/sub RC/=70 ns, T=25/spl deg/C. This chip has been fabricated using a 0.18 /spl mu/m twin-well CMOS process with KrF lithography having transistor channel lengths of 0.32(n)/0.40(p)/spl mu/m and low resistance TiSi/sub 2/ wordlines.","PeriodicalId":399030,"journal":{"name":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","volume":"205 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 Symposium on VLSI Circuits. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1996.507731","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

An experimental 16 Mb DRAM for giga scale densities with a charge-amplifying boosted sensing (CABS) scheme and a new I/O large gain current sense amplifier using a cross-coupled current mirror control scheme achieves a t/sub RAC/ of 28 ns and an average operating current of 22 mA at V/sub CC/=1.5 V, t/sub RC/=70 ns, T=25/spl deg/C. This chip has been fabricated using a 0.18 /spl mu/m twin-well CMOS process with KrF lithography having transistor channel lengths of 0.32(n)/0.40(p)/spl mu/m and low resistance TiSi/sub 2/ wordlines.
千兆位dram的低电压高速电路设计
采用电荷放大增强感测(CABS)方案和采用交叉耦合电流镜像控制方案的新型I/O大增益电流感测放大器,在V/sub CC/=1.5 V, t/sub RC/=70 ns, t =25/spl度/C时,t/sub RAC/的平均工作电流为28 ns,平均工作电流为22 mA。该芯片采用0.18 /spl mu/m双阱CMOS工艺,KrF光刻,晶体管通道长度为0.32(n)/0.40(p)/spl mu/m,低电阻TiSi/ sub2 / wordlines。
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