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Hot Carrier Reliability Considerations For High Performance Submicron Mosfet's 高性能亚微米Mosfet热载流子可靠性考虑
Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications Pub Date : 1997-06-03 DOI: 10.1109/VTSA.1997.614921
Ho-Chung Huang, Jiuun-Jer Yang, Talee Yu, K. Young, K. Chiu
{"title":"Hot Carrier Reliability Considerations For High Performance Submicron Mosfet's","authors":"Ho-Chung Huang, Jiuun-Jer Yang, Talee Yu, K. Young, K. Chiu","doi":"10.1109/VTSA.1997.614921","DOIUrl":"https://doi.org/10.1109/VTSA.1997.614921","url":null,"abstract":"The criteria of HC reliability strongly affect the choice of the device structure as well as performance. Based on different considerations, various device parameters such as transconductance, linear region drain current degradation and saturation current degradation. can be used as deciding monitors for the device hot carrier lifetime. In this study, the constraints of HC reliability on device structures and performance for different technology ranging from 0.5pm/5V to 0.25pm/2.5V *are investigated and compared. The suitable drain structure is different for each generation. The choice depends on the monitoring device parameter and performanceireliability tradeoff.","PeriodicalId":392409,"journal":{"name":"Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124396105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Noise Suppression In Low Voltage Differential I/O 低电压差分I/O中的噪声抑制
Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications Pub Date : 1997-06-03 DOI: 10.1109/VTSA.1997.614771
T. Haulin, M. Hedberg
{"title":"Noise Suppression In Low Voltage Differential I/O","authors":"T. Haulin, M. Hedberg","doi":"10.1109/VTSA.1997.614771","DOIUrl":"https://doi.org/10.1109/VTSA.1997.614771","url":null,"abstract":"Tord Haulin and Mats Hedberg Ericsson Telecom, Stockholm, Sweden Various kinds of noise sources induce distortion in electronic equipment signals. Generally for electrical signals, the longer distance a signal is transmitted, the more noise it is subjected to. With today's high frequencies and low voltages, noise management has become much more important, also for signal transmission over shorter distances. Older signalling standards rely on large signal swings and voltage margins within 5V and 3.3V supply voltage ranges. With new types of IiO such as GLVDS [ 11 (Ground referenced, impedance matched, Low Voltage Differential Signal), operating at very low voltages, the VO itself must be much more robust to noise. Low supply voltages reduce the voltage margin to signal degradation due to various clamping phenomena. By careful design of both receivers and transmitters however, noise suppression performance can be made even superior to that of IiOs operating with higher voltages.","PeriodicalId":392409,"journal":{"name":"Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122672783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-power High-speed Complementary Gaas Dynamic Logic Circuit Design 低功耗高速互补Gaas动态逻辑电路设计
Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications Pub Date : 1997-06-03 DOI: 10.1109/VTSA.1997.614910
K. Shehata, D. Fouts
{"title":"Low-power High-speed Complementary Gaas Dynamic Logic Circuit Design","authors":"K. Shehata, D. Fouts","doi":"10.1109/VTSA.1997.614910","DOIUrl":"https://doi.org/10.1109/VTSA.1997.614910","url":null,"abstract":"Complementary Gallium Arsenide (CGaAs) dynamic logic circuits, including Domino, N-P Domino, and Two-Phase Dynamic FET Logic have been designed, simulated, implemented and compared against GaAs complementary static logic. TPDL circuits are the fastest (up to 2.38 GKZ) and have the lowest power consumption ever reported in this technology (0.01 pWIMHilgate).","PeriodicalId":392409,"journal":{"name":"Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122047584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study Of Integration Issues Of Ti Salicide Process With Preamorphization For Sub-0.18 /spl mu/m Gate Length CMOS Technologies 栅极长度低于0.18 /spl mu/m的CMOS技术中预非晶化盐化钛工艺集成问题的研究
Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications Pub Date : 1997-06-03 DOI: 10.1109/VTSA.1997.614719
J. Kittl, A. Chatterjee, I. Chen, G. Dixit, P. P. Apte, D. Prinslow, Q. Hong
{"title":"Study Of Integration Issues Of Ti Salicide Process With Preamorphization For Sub-0.18 /spl mu/m Gate Length CMOS Technologies","authors":"J. Kittl, A. Chatterjee, I. Chen, G. Dixit, P. P. Apte, D. Prinslow, Q. Hong","doi":"10.1109/VTSA.1997.614719","DOIUrl":"https://doi.org/10.1109/VTSA.1997.614719","url":null,"abstract":"A study of integration issues of Ti SALICIDE with preaniorphization for sub-0.18 pm gate length 1.8V CMOS technologies is presented, studying process window and process optimization in terms of the most relevant device parameters and device performance. The process space explored included As pre-amorphization implant (PAI) energy, Ti thickness, silicide rapid thermal processing (RTP) formation temperature and time, silicide RTP anneal tcmperature and time, and two post-SALICIDE flows: low temperature (T300\"C except RTP steps) and high temperature (T up to 700°C). An optimized process was obtained with a -45 nm thin silicide, using shallow preamorphization, short anneal time, optimized RTP, and low temperature post-SALICIDE processing, obtaining optimal silicide to source/drain contact resistance (&), source and drain series resistance (RsD), and drive current (IDRIVE), with low 0.16 pm gate sheet resistance, low diode leakage and no gate to S/D bridging.","PeriodicalId":392409,"journal":{"name":"Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129559042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Integrated Ferroelectric Technology For Nonvolatile 非易失性集成铁电技术
Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications Pub Date : 1997-06-03 DOI: 10.1109/VTSA.1997.614749
T. Sumi
{"title":"Integrated Ferroelectric Technology For Nonvolatile","authors":"T. Sumi","doi":"10.1109/VTSA.1997.614749","DOIUrl":"https://doi.org/10.1109/VTSA.1997.614749","url":null,"abstract":"Nonvolatile memory utilizing ferroelectric material is expected to be the ultimate memory due to its theoretical low power operation and fast access. We integrated a ferroelectric thin film using a standard complementary metal-oxidesemiconductor (CMOS) process and evaluated its basic characteristics and reliability including endurance and imprint effect. The film was prepared using a spin-on sol-gel method No effects of the ferroelectric process on the CM015 transistors were observed. Design of ferroelectric memory cells and applications of the ferroelectric nonvolatile memoiry have been reviewed. Introduction Commonly utilized semiconductor memories, are volatile memories such as a DRAM and an SRAM. [n contrast, nonvolatile memory devices include EPROM, EEPROM and Flash EEPROM. Flash EEPROM has recently increased its market share &e to a much faster erasing operation and a smaller cell size than EEPROM. A ferroelectric memory is expected to be the ultimate memory because it is a much faster nonvolatile random access memory (RAM) with less power consumption than the other nonvolatile memories. Perovskite structure is known to be ferroelectric. An atom at the center of a lattice causes polarization by a shift from an electrically neutral state according to the extemal electric field. It is assumed to be an \"atomic switch\". An EEPlROM uses electron injection to a floating gate through thin silicon oxide to create a logic high or logic low state. Therefore it needs a relatively high voltage and a long time to write the operation. On the other hand a ferroelectric memory is in principle fast and operates at low voltage because of its atomic switch. There is an EEPROM that can operate at a low supply voltage with Table 1. Nonvolatile memories.","PeriodicalId":392409,"journal":{"name":"Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130484616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Delayed Synchronizer In High-speed Memory Applications 高速存储器应用中的延迟同步器
Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications Pub Date : 1997-06-03 DOI: 10.1109/VTSA.1997.614732
Sanghun Jung, Wonchan Kim
{"title":"A Delayed Synchronizer In High-speed Memory Applications","authors":"Sanghun Jung, Wonchan Kim","doi":"10.1109/VTSA.1997.614732","DOIUrl":"https://doi.org/10.1109/VTSA.1997.614732","url":null,"abstract":"4 b s h c t A delayed synchronizer applicable for high-speed synchronous memories will be d iscussed, which consists of a complementary delaytiime sensor/generator and a voltage comparator. B:y iising the charge pump scheme, it enables the internal clock to be synchronized within 1 external clock cycle. The clock skew is kept less than 50ps for rising edges and 250ps for falling edges for clock frc-quency of 250MHz.","PeriodicalId":392409,"journal":{"name":"Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134249699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High Performance Gate-all-around TFT(GAT) For High-density, Low-voltage-operation, And Low-power Srams 用于高密度、低电压、低功耗ram的高性能栅极全能TFT(GAT)
Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications Pub Date : 1997-06-03 DOI: 10.1109/VTSA.1997.614743
S. Miyamoto, S. Maegawa, S. Maeda, T. Ipposhi, H. Kuriyama, T. Nishimura
{"title":"High Performance Gate-all-around TFT(GAT) For High-density, Low-voltage-operation, And Low-power Srams","authors":"S. Miyamoto, S. Maegawa, S. Maeda, T. Ipposhi, H. Kuriyama, T. Nishimura","doi":"10.1109/VTSA.1997.614743","DOIUrl":"https://doi.org/10.1109/VTSA.1997.614743","url":null,"abstract":"The gate-all-around thin-film transistor (GAT) can suppress the individual performance variation. The suppression mechanism of the individual performance variation in the GAT was investigated using a poly-Si TFT simulator. The GAT is more effective on the decrease of the individual performance variation than the single-gate TFT in low-voltage operation. Moreover, the OFF-current of the GAT is almost the same as that of the single-gate TFT with the LDD. The GAT is an attractive candidate to achieve high-density, low-voltageoperation, and low-power SRAMs.","PeriodicalId":392409,"journal":{"name":"Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications","volume":"350 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132641067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ultra-thin Oxide With Atomically Smooth Interfaces 具有原子光滑界面的超薄氧化物
Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications Pub Date : 1997-06-03 DOI: 10.1109/VTSA.1997.614753
A. Chin, Wei-Chen Chen, R. Kao, B. Lin, T. Chang, Chia-Chun Tsai, Jian-Fu Huang
{"title":"Ultra-thin Oxide With Atomically Smooth Interfaces","authors":"A. Chin, Wei-Chen Chen, R. Kao, B. Lin, T. Chang, Chia-Chun Tsai, Jian-Fu Huang","doi":"10.1109/VTSA.1997.614753","DOIUrl":"https://doi.org/10.1109/VTSA.1997.614753","url":null,"abstract":"Native oxide is an important issue for ultra-thin oxide, which is strongly related to the gate oxide integrity such as QBD, interface scattering, etc. We have designed a leak-tight low-pressure oxidation system to desorb the native oxide in-situ. Atomically flat interfaces between oxide and Si are obtained for oxide thicknesses of 11 and 38 A. Because of the smooth interface and good thickness uniformity of oxide, both high-field electron mobility and oxide breakdown behavior are much improved.","PeriodicalId":392409,"journal":{"name":"Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131181331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Area-efficient VDD-to-vSS ESD Clamp Circuit By Using Substrate-triggering Field-oxide Device (STFFOD) For Whole-chip ESD Protection 利用基板触发场氧化器件(STFFOD)实现全芯片ESD保护的面积高效VDD-to-vSS ESD箝位电路
Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications Pub Date : 1997-06-03 DOI: 10.1109/VTSA.1997.614730
M. Ker
{"title":"Area-efficient VDD-to-vSS ESD Clamp Circuit By Using Substrate-triggering Field-oxide Device (STFFOD) For Whole-chip ESD Protection","authors":"M. Ker","doi":"10.1109/VTSA.1997.614730","DOIUrl":"https://doi.org/10.1109/VTSA.1997.614730","url":null,"abstract":"A novel ~ substrate-triggering ~ _ _ field-oxide ~ device (STFOD) is proposed to form an area-efficient ESD clamp circuit for whole-chip ESD protection in submicron CMOS technology. Experimental results in a 0.6-pm CMOS process have verified that this STFOD can provide four-times higher ESD robustness in per unit layout area as comparing to ihe previous works with the NMOS device. This design has been practically implemented in an 8-bits DAC chip to provide a real whole-chip ESD protection of above 4KV.","PeriodicalId":392409,"journal":{"name":"Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116466092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Design Rule Related Defects Formation 与设计规则相关的缺陷形成
Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications Pub Date : 1997-06-03 DOI: 10.1109/VTSA.1997.614745
Y. Hsieh, B. Tsui
{"title":"Design Rule Related Defects Formation","authors":"Y. Hsieh, B. Tsui","doi":"10.1109/VTSA.1997.614745","DOIUrl":"https://doi.org/10.1109/VTSA.1997.614745","url":null,"abstract":"Abstract Formation of implantation induced tertiary defects is reported to be closely related to the design rule of poly-Si (on field oxide) to active area distance. Leakage current measurements of N+/P-type junctions was used to characterize the defect density of a variety of layout structures. Material analyses were also conducted to reveal the defect natures in Si crystal lattices and occurring probability of dislocations.","PeriodicalId":392409,"journal":{"name":"Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123562126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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