{"title":"An automatic testing and diagnosis for FPGAs","authors":"A. Doumar, Hideo Ito","doi":"10.1109/PRDC.1999.816211","DOIUrl":"https://doi.org/10.1109/PRDC.1999.816211","url":null,"abstract":"This paper presents a new design for testing and diagnosing the SRAM-based field programmable gate arrays (FPGA). By slightly modifying the original FPGA's SRAM memory, the new architecture permits the configuration data to be looped on a chip. Then the full testing and diagnosing of the FPGA are achieved by loading typically only one testing configuration datum (carefully chosen) instead of loading the total required configurations data (which is a very slow process) in the normal cases. Other configurations data are obtained by shifting the first one inside the chip. Consequently the test becomes faster. This method does not need a large outside memory (off-chip memory) for the test. The evaluation proves that this method becomes very interesting when the complexity of the configurable blocks (CLBs) or the chip size increase.","PeriodicalId":389294,"journal":{"name":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123348179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dependability issues in mobile distributed system","authors":"Heimo Laamanen, T. Alanko, K. Raatikainen","doi":"10.1109/PRDC.1999.816206","DOIUrl":"https://doi.org/10.1109/PRDC.1999.816206","url":null,"abstract":"The article discusses dependability issues in Distributed Systems comprising mobile hosts and wireless data communications (Mobile Distributed Systems). By enabling motion and location independence wireless data communications and mobile hosts allow information access that may occur any time and any place. We show that location and time significantly affect the dependability concept of distributed systems. We demonstrate that the traditional dependability concept is not adequate for Mobile Distributed Systems. Therefore, we enhance the dependability concept to be suitable for Mobile Distributed Systems by extending the definitions of availability and reliability. In addition, we introduce a new attributed of dependability called serveability, which addresses the dependability of the service of Mobile Distributed Systems in a way that a nomadic end-user measures it. We also propose a model of Mobile Distributed Systems that helps the designers and programmers of Mobile Distributed Systems to build distributed systems that offer the best obtainable dependability everywhere and at any time.","PeriodicalId":389294,"journal":{"name":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125970603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault-tolerant routing algorithms based on optimal path matrices","authors":"F. Gao, Zhongcheng Li","doi":"10.1109/PRDC.1999.816233","DOIUrl":"https://doi.org/10.1109/PRDC.1999.816233","url":null,"abstract":"Presents a new concept - optimal path matrices (OPMs) - for fault-tolerant routing on hypercube multicomputers. OPMs stored on each node of a hypercube hold the fault information and indicate whether there is an optimal path from the node to a destination. Two fault-tolerant routing algorithms based on OPMs are proposed in order to maintain the matrices and to route messages from sources to destinations. One is a routing algorithm based on OPMs, which are filled with pre-collected information through information exchange between neighbors. It can easily establish a path for a message, and the length of the path is no greater than the Hamming distance between the source and the destination of the message plus two. The other routing algorithm is a modified depth-first search algorithm, which adopts a dynamic learning strategy to fill OPMs during normal message transmission and can find almost all the optimal paths. The memory overhead is n/sup 2/ words on each node of an n-dimensional hypercube.","PeriodicalId":389294,"journal":{"name":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121237189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardware fault tolerance in arithmetic coding for data compression","authors":"G. Redinbo","doi":"10.1109/PRDC.1999.816214","DOIUrl":"https://doi.org/10.1109/PRDC.1999.816214","url":null,"abstract":"New fault tolerance techniques are presented for protecting a lossless compression algorithm, arithmetic coding, whose recursive nature makes it vulnerable to temporary hardware failures. The fundamental arithmetic operations are protected by low-cost residue codes, employing fault tolerance in multiplications and additions. Additional fault-tolerant design techniques are developed to protect other critical steps such as normalization and rounding, bit stuffing and index selection. For example, the decoding step that selects the next symbol is checked by comparing local values with estimates already calculated in other parts of the decoding structure. Bit stuffing, a procedure for limiting very long carry propagations, is checked through modified residue values, whereas normalization and rounding after multiplication are protected by efficiently modifying the multiplier to produce residue segments.","PeriodicalId":389294,"journal":{"name":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128149937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel fault tolerant approach for SRAM-based FPGAs","authors":"Jian Xu, P. Si, Wei-Kang Huang, F. Lombardi","doi":"10.1109/PRDC.1999.816210","DOIUrl":"https://doi.org/10.1109/PRDC.1999.816210","url":null,"abstract":"This paper presents a novel fault tolerant approach for SRAM-based FPGAs. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs and interconnects are considered. The fault tolerant routing procedure under this novel approach is simple and less time-consuming. We provide the simulation results and show that the proposed approach has lower overhead than previous methods found in technical literature.","PeriodicalId":389294,"journal":{"name":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133737817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The effect of interconnect schemes on the dependability of a modular multi-processor system with shared resources","authors":"F.M.G. Dorenberg, Huesung Kim, Arun Kumar Somani","doi":"10.1109/PRDC.1999.816219","DOIUrl":"https://doi.org/10.1109/PRDC.1999.816219","url":null,"abstract":"AlliedSignal's Avionics & Lighting business unit is expanding the performance of its flight safety avionics by means of functional integration (added functionality enabled by exchanging information between traditionally stand-alone subsystems), as well as physical integration (sharing of system resources) and full dual redundancy. Major performance goals of this integrated modular architecture are a significant increase in system dispatchability and reduction of the loss-of-function probability of individual junctions. Success of this architectural migration depends on the scheme that is used to fully interconnect the various processing and input/output modules. Two of the considered interconnect schemes are discussed: a dual LAN and a dual-dual LAN. In both schemes, all modules can receive data from all LANs. In the prior scheme, all system modules have time-multiplexed transmit privileges on both LANs. In the latter scheme (patent pending), the modules are grouped into two identical sets. The modules in a set can only transmit on two of the four LANs. Dependability of the system has been modeled and analyzed with the HIMAP tool for both schemes, and the results are presented.","PeriodicalId":389294,"journal":{"name":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130348162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parity sensitive comparators","authors":"G. Fabregat, José V. Martí, G. Leon","doi":"10.1109/PRDC.1999.816212","DOIUrl":"https://doi.org/10.1109/PRDC.1999.816212","url":null,"abstract":"Parity sensitive comparators are a new type of comparators designed to take advantage of the parity information present in most buses. Instead of simply comparing the signals carried by the buses, parity information is used to select the probably correct output in case of mismatch, thus avoiding an important percentage of errors to stop system functioning. These devices verify parity for each pair of compared groups and discard erroneous data when comparing, propagating the probably correct data and signaling the fact with a \"recoverable error\" output signal. Benefits of parity sensitive comparators are analyzed by means of a deep probabilistic study of the \"parity bit per data byte\" case that shows how they are able to recover more than the 97% of errors signaled by classical comparators. The output information of the comparators is also described, as well as its uses according to the level of reliability required.","PeriodicalId":389294,"journal":{"name":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129688613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FBD: a fault-tolerant buffering disk system for improving write performance of RAID5 systems","authors":"H. Yokota, Masanori Goto","doi":"10.1109/PRDC.1999.816218","DOIUrl":"https://doi.org/10.1109/PRDC.1999.816218","url":null,"abstract":"The parity calculation technique of the RAID5 provides high reliability, efficient disk space usage, and good read performance for parallel-disk-array configurations. However, it requires four disk accesses for each write request. The write performance of a RAID5 is therefore poor compared with its read performance. We propose a buffering system to improve write performance while maintaining the reliability of the total system. The buffering system uses two to four disks clustered into two groups, primary and backup. Write performance is improved by sequential accesses of the primary disks without interruption and by reduction of irrelevant disk accesses for the RAID5 by packing. The backup disks are used to tolerate a disk failure and to accept read requests for data stored in the buffering system so as not to disturb sequential accesses in the primary disks. We developed an experimental system using an off-the-shelf personal computer and disks, and a commercial RAID5 system. The experiments indicate that the buffering system considerably improves both system throughput and average response time.","PeriodicalId":389294,"journal":{"name":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121099484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimal checkpointing and rollback strategies with media failures: statistical estimation algorithms","authors":"T. Dohi, S. Osaki, N. Kaio","doi":"10.1109/PRDC.1999.816225","DOIUrl":"https://doi.org/10.1109/PRDC.1999.816225","url":null,"abstract":"This paper considers two stochastic models for a file recovery action with checkpoint generations when two kinds of failures; system failure and media failure, occur according to a homogeneous Poisson process and a renewal process, respectively. For the unknown media failure time distribution, we develop statistical nonparametric algorithms to estimate the optimal checkpoint intervals which maximize the system availabilities. The algorithms proposed are based on the corresponding total time on test (TTT) statistics to the media failure time distribution, and can provide strongly consistent estimates from its sample data.","PeriodicalId":389294,"journal":{"name":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129566419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A simulated fault injection tool for dependable VoD application design","authors":"L. Romano, G. Capuozzo, A. Mazzeo, N. Mazzocca","doi":"10.1109/PRDC.1999.816226","DOIUrl":"https://doi.org/10.1109/PRDC.1999.816226","url":null,"abstract":"This work presents a simulation-based tool for dependability-oriented design of Video on Demand (VoD) applications. The tool is organized in a layered architecture, so that simulation models can be built and detailed according to a hierarchical and modular approach. The higher layer, namely the Application Level, provides a variety of objects to rapidly model fundamental components typically found in most VoD systems. The lower level, namely the Network Level, consists of the basic building blocks needed to represent the communication infrastructure of a distributed system. The paper illustrates how to combine the tool's built-in objects, in order to construct a simulated model of a generic multimedia application. Some of the potentialities of the tool are then demonstrated by performing dependability evaluation of a real VoD system prototype. Fault injection experiments are conducted on a simulated model of DiVA, a distributed architecture for VoD applications, currently under development at the University of Naples.","PeriodicalId":389294,"journal":{"name":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","volume":"53 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131910203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}