{"title":"一种基于sram的fpga容错方法","authors":"Jian Xu, P. Si, Wei-Kang Huang, F. Lombardi","doi":"10.1109/PRDC.1999.816210","DOIUrl":null,"url":null,"abstract":"This paper presents a novel fault tolerant approach for SRAM-based FPGAs. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs and interconnects are considered. The fault tolerant routing procedure under this novel approach is simple and less time-consuming. We provide the simulation results and show that the proposed approach has lower overhead than previous methods found in technical literature.","PeriodicalId":389294,"journal":{"name":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A novel fault tolerant approach for SRAM-based FPGAs\",\"authors\":\"Jian Xu, P. Si, Wei-Kang Huang, F. Lombardi\",\"doi\":\"10.1109/PRDC.1999.816210\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a novel fault tolerant approach for SRAM-based FPGAs. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs and interconnects are considered. The fault tolerant routing procedure under this novel approach is simple and less time-consuming. We provide the simulation results and show that the proposed approach has lower overhead than previous methods found in technical literature.\",\"PeriodicalId\":389294,\"journal\":{\"name\":\"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-12-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PRDC.1999.816210\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1999 Pacific Rim International Symposium on Dependable Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PRDC.1999.816210","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel fault tolerant approach for SRAM-based FPGAs
This paper presents a novel fault tolerant approach for SRAM-based FPGAs. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs and interconnects are considered. The fault tolerant routing procedure under this novel approach is simple and less time-consuming. We provide the simulation results and show that the proposed approach has lower overhead than previous methods found in technical literature.