A. Azevedo, R. Cornea, I. Issenin, R. Gupta, N. Dutt, A. Nicolau, A. Veidenbaum
{"title":"Architectural and compiler strategies for dynamic power management in the COPPER project","authors":"A. Azevedo, R. Cornea, I. Issenin, R. Gupta, N. Dutt, A. Nicolau, A. Veidenbaum","doi":"10.1109/IWIA.2001.955194","DOIUrl":"https://doi.org/10.1109/IWIA.2001.955194","url":null,"abstract":"For a range of embedded system applications in mission critical and energy constrained scenarios, it is important to be able to dynamically control power consumption in response to changing power availability. The authors present their approach to dynamic adaptation of system power consumption and application performance through microarchitectural and software strategies. In particular, they discuss techniques for compiler controlled dynamic register file reconfiguration and profile-driven dynamic clock frequency and voltage scaling. The authors evaluate the effectiveness of power scheduling heuristics based on these techniques in complying with desired power and performance constraints for a given application.","PeriodicalId":388942,"journal":{"name":"2001 Innovative Architecture for Future Generation High-Performance Processors and Systems","volume":"10 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134026733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Nakajo, M. Ishii, J. Yamamoto, T. Kudo, T. Yokoyama, J. Tsuchiya, H. Amano
{"title":"Cache coherence protocol for home proxy cache on RHiNET and its preliminary performance estimation","authors":"H. Nakajo, M. Ishii, J. Yamamoto, T. Kudo, T. Yokoyama, J. Tsuchiya, H. Amano","doi":"10.1109/IWIA.2001.955197","DOIUrl":"https://doi.org/10.1109/IWIA.2001.955197","url":null,"abstract":"LASN (Local Area System Network) is a new class of networks which has the advantages of both SANS and LANs. RHiNET (RWCP high performance network) is the first network designed with the concepts of an LASN. A prototype called RHiNET-1 using 1.33 Gbps optical interconnections is available for research on cluster computing. In the case of implementing distributed shared-memory system on a cluster system, software based cache memory is used in order to reduce the number of accesses to shared-memory and a large amount of communication in the network. We have proposed Home Proxy Cache which keeps copies of pages in home memory in order to avoid I/O bus bottleneck when there are many accesses from the other nodes to the home memory. In this paper, a network interface of RHiNET is introduced and the detailed coherence protocol for a distributed shared-memory system is presented. The protocol will be implemented in the RHiNET network interface. We have estimated effectiveness of Home Proxy Cache with RHiNET-1 and RHiNET-2 in cases of Read Miss and Write Miss to Cache Memory.","PeriodicalId":388942,"journal":{"name":"2001 Innovative Architecture for Future Generation High-Performance Processors and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131619094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}