2001 Innovative Architecture for Future Generation High-Performance Processors and Systems最新文献

Power efficient instruction cache for wide-issue processors 用于大问题处理器的高效指令缓存

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems Pub Date : 2001-01-18 DOI: 10.1109/IWIA.2001.955192

A.-M. Badulescu, A. Veidenbaum

引用次数: 5

An efficient algorithm for pointer-to-array access conversion for compiling and optimizing DSP applications 一种用于编译和优化DSP应用程序的指针到数组访问转换的有效算法

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems Pub Date : 1900-01-01 DOI: 10.1109/IWIA.2001.955200

Robert A. van Engelen, K. Gallivan

{"title":"An efficient algorithm for pointer-to-array access conversion for compiling and optimizing DSP applications","authors":"Robert A. van Engelen, K. Gallivan","doi":"10.1109/IWIA.2001.955200","DOIUrl":"https://doi.org/10.1109/IWIA.2001.955200","url":null,"abstract":"The complexity of Digital Signal Processing (DSP) applications has been steadily increasing due to advances in hardware design for embedded processors. To meet critical power consumption and timing constraints, many DSP applications are hand-coded in assembly. Because the cost of hand-coding is becoming prohibitive for developing an embedded system, there is a trend toward the use of high-level programming languages, particularly C, and the use of optimizing compilers for software development. Consequently, more than ever there is a need for compilers to optimize DSP application to make effective use of the available hardware resources. Existing DSP codes are often riddled with pointer-based data accesses, because DSP programmers have the mistaken belief that a compiler will always generate better target code. The use of extensive pointer arithmetic makes analysis and optimization difficult for compilers for modern DSPs with regular architectures and large homogeneous registers sets. In this paper, we present a novel algorithm for converting pointer-based code to code with explicit array accesses. The conversion enables a compiler to perform data flow analysis and loop optimizations on DSP codes.","PeriodicalId":388942,"journal":{"name":"2001 Innovative Architecture for Future Generation High-Performance Processors and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128224906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Present status of development of the Earth Simulator 地球模拟器的发展现状

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems Pub Date : 1900-01-01 DOI: 10.1109/IWIA.2001.955201

M. Yokokawa

引用次数: 17

Characteristics of loop unrolling effect: software pipelining and memory latency hiding 循环展开效果的特点:软件流水线化和内存延迟隐藏

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems Pub Date : 1900-01-01 DOI: 10.1109/IWIA.2001.955198

S. Hiroyuki, Y. Teruhiko

引用次数: 6

Wrapped system call in communication and execution fusion OS: CEFOS 通信与执行融合操作系统CEFOS中的封装系统调用

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems Pub Date : 1900-01-01 DOI: 10.1109/IWIA.2001.955199

Hiroshi Nakayama, Takuya Tanabayashi, Makoto Amamiya

引用次数: 0

Cache-In-Memory Cache-In-Memory

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems Pub Date : 1900-01-01 DOI: 10.1109/IWIA.2001.955191

J. T. Zawodny, P. Kogge

引用次数: 6

An architecture of on-chip-memory multi-threading processor 片上内存多线程处理器的结构

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems Pub Date : 1900-01-01 DOI: 10.1109/IWIA.2001.955202

T. Matsuzaki, H. Tomiyasu, M. Amamiya

引用次数: 2

An approach towards an analytical characterization of locality and its portability 一种局部性及其可移植性的分析表征方法

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems Pub Date : 1900-01-01 DOI: 10.1109/IWIA.2001.955195

G. Bilardi, E. Peserico

{"title":"An approach towards an analytical characterization of locality and its portability","authors":"G. Bilardi, E. Peserico","doi":"10.1109/IWIA.2001.955195","DOIUrl":"https://doi.org/10.1109/IWIA.2001.955195","url":null,"abstract":"The evolution of computing technology towards the ultimate physical limits makes communication the dominant cost of computing. It would then be desirable to have a framework for the study of locality, which we define as the property of an algorithm that enables implementations with reduced communication overheads. We discuss the issue of useful characterizations of the locality of an algorithm with reference to both single machines and classes of machines. We then consider the question of portability of locality. We illustrate the proposed approach with its application to the study of temporal locality, the property of an algorithm that enables efficient implementations on machines where memory accesses have a variable latency, depending on the location being accessed. We discuss how, for a fixed operation schedule, temporal locality can be characterized for interesting classes of uniform hierarchical machines by a set of metrics, the width lengths of the schedule. Moreover, a portable memory management of any schedule can be obtained for such classes of machines. The situation becomes more complex when the schedule is a degree of freedom of the implementation. Then, while some computations do admit a single schedule, optimal across many machines, this is not always the case. Thus, in general, only the less stringent notion of portability based on parametrized schedules can be pursued. Correspondingly, a concise characterization of temporal locality becomes harder to achieve and still remains an open problem.","PeriodicalId":388942,"journal":{"name":"2001 Innovative Architecture for Future Generation High-Performance Processors and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121158874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Power reduction in superscalar datapaths through dynamic bit-slice activation 通过动态位片激活来降低超标量数据路径的功耗

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems Pub Date : 1900-01-01 DOI: 10.1109/IWIA.2001.955193

Dmitry Ponomarev, Gurhan Kucuk, K. Ghose

引用次数: 5

Pipelined memory hierarchies: scalable organizations and application performance 流水线内存层次结构:可伸缩组织和应用程序性能

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems Pub Date : 1900-01-01 DOI: 10.1109/IWIA.2001.955196

G. Bilardi, K. Ekanadham, P. Pattnaik

{"title":"Pipelined memory hierarchies: scalable organizations and application performance","authors":"G. Bilardi, K. Ekanadham, P. Pattnaik","doi":"10.1109/IWIA.2001.955196","DOIUrl":"https://doi.org/10.1109/IWIA.2001.955196","url":null,"abstract":"The time to perform a random access to main memory has been increasing for decades relative to processor speed and is currently of the order of a few hundred cycles. To alleviate this problem, one resorts to memory organizations that are hierarchical to exploit locality of the computation, and pipelinable to exploit parallelism. The goal of the study is to begin a systematic exploration of the performance advantages of such memories, achieving scalability even when the underlying principles are pushed to the limit permitted by physical laws. First, we propose memory organizations with the ability to accept requests at a constant rate without significantly affecting the latency of individual requests, which is within a constant factor of the minimum value achievable under fundamental physical constraints. Second, we discuss how the pipeline capability can be effectively exploited by memory management techniques in order to reduce execution time for applications. We conclude by outlining the issues that require further work in order to pursue systematically the potential of pipelined hierarchical memories.","PeriodicalId":388942,"journal":{"name":"2001 Innovative Architecture for Future Generation High-Performance Processors and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121684687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2