Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors最新文献

Contention-conscious transaction ordering in embedded multiprocessors 嵌入式多处理器中具有竞争意识的事务排序

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors Pub Date : 2000-07-10 DOI: 10.1109/ASAP.2000.862398

M. Khandelia, S. Bhattacharyya

引用次数: 7

Block-update parallel processing QRD-RLS algorithm for throughput improvement with low power consumption 块更新并行处理QRD-RLS算法在低功耗下提高吞吐量

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors Pub Date : 2000-07-10 DOI: 10.1109/ASAP.2000.862393

Lijun Gao, K. Parhi

{"title":"Block-update parallel processing QRD-RLS algorithm for throughput improvement with low power consumption","authors":"Lijun Gao, K. Parhi","doi":"10.1109/ASAP.2000.862393","DOIUrl":"https://doi.org/10.1109/ASAP.2000.862393","url":null,"abstract":"In this paper, a block-update parallel processing algorithm is proposed for increasing the throughput of the CORDIC-based QRD-RLS filtering with low power consumption. The proposed algorithm employs single-state-update parallel processing, and with this algorithm, the throughput of a block-by-block weight-update QRD-RLS filter can be increased at the cost of linear increase in hardware resource. However, the proposed algorithm does not change the iteration bounds and clock frequency of the QRD-RLS filters. As a result, the functional units need not be pipelined and the power consumption only increases linearly instead of quadratically. Due to non-pipelining and less power consumption, a higher folding factor can be used for a folding transformation and a great reduction in hardware resource can be achieved without exceeding the physical limitation on pipelining level and power density. Therefore, the proposed algorithm can serve as an important stage in designing and mapping a QRD-RLS filter onto physical hardware or computing resources, and thus is better for both ASIC chip design and parallel computing when block-by-block weight-update is applicable.","PeriodicalId":387956,"journal":{"name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127719175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Architecture of an image rendering co-processor for MPEG-4 systems 用于MPEG-4系统的图像渲染协处理器体系结构

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors Pub Date : 2000-07-10 DOI: 10.1109/ASAP.2000.862374

Mladen Berekovic, P. Pirsch, T. Selinger, Kai-Immo Wels, C. Miro, A. Lafage, C. Heer, G. Ghigo

{"title":"Architecture of an image rendering co-processor for MPEG-4 systems","authors":"Mladen Berekovic, P. Pirsch, T. Selinger, Kai-Immo Wels, C. Miro, A. Lafage, C. Heer, G. Ghigo","doi":"10.1109/ASAP.2000.862374","DOIUrl":"https://doi.org/10.1109/ASAP.2000.862374","url":null,"abstract":"The TANGRAM VLSI co-processor is intended as a building block for use in system-on-chip (SOC) designs for the versatile MPEG-4 multimedia standard. It is designed to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. This includes warping and alpha blending of multiple full-screen video textures in real-lime. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or software support for different video-formats. Communication to a host CPU and video decoding hardware is done via the very common PI-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 /spl mu/ standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm/sup 2/ overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main Profile@Layer3 scenes (CCIR).","PeriodicalId":387956,"journal":{"name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors","volume":"39 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131894500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Partitioning conditional data flow graphs for embedded system design 嵌入式系统设计中条件数据流图的划分

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors Pub Date : 2000-07-10 DOI: 10.1109/ASAP.2000.862404

M. Auguin, L. Bianco, Laurent Capella, E. Gresset

引用次数: 8

A Booth multiplier accepting both a redundant or a non redundant input with no additional delay 布斯乘法器，接受冗余或非冗余输入，没有额外的延迟

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors Pub Date : 2000-07-10 DOI: 10.1109/ASAP.2000.862391

M. Daumas, D. Matula

引用次数: 28

High level modeling for parallel executions of nested loop algorithms 嵌套循环算法并行执行的高级建模

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors Pub Date : 2000-07-10 DOI: 10.1109/ASAP.2000.862380

E. Deprettere, E. Rijpkema, P. Lieverse, B. Kienhuis

引用次数: 8

A multiplication-free parallel architecture for affine transformation 仿射变换的无乘法并行结构

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors Pub Date : 2000-07-10 DOI: 10.1109/ASAP.2000.862375

Wael Badawy, M. Bayoumi

引用次数: 11

Integration of high-performance ASICs into reconfigurable systems providing additional multimedia functionality 将高性能asic集成到可重构系统中，提供额外的多媒体功能

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors Pub Date : 2000-07-10 DOI: 10.1109/ASAP.2000.862379

H. Blume, Hans-Martin Blüthgen, C. Henning, Patrick Osterloh

引用次数: 7

Control for high-speed PE arrays 高速PE阵列控制

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors Pub Date : 2000-07-10 DOI: 10.1109/ASAP.2000.862395

M. Herbordt, Honghai Zhang, Calvin Lin, H. Rao, J. Cravy

引用次数: 1

Tradeoff analysis and architecture design of a hybrid hardware/software sorter 混合硬件/软件分选器的权衡分析与架构设计

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors Pub Date : 2000-07-10 DOI: 10.1109/ASAP.2000.862400

M. Bednara, O. Beyer, J. Teich, R. Wanka

引用次数: 17