A multiplication-free parallel architecture for affine transformation

Abstract

This paper presents a novel low power parallel architecture for computing affine transformation (AT). It is based on a new multiplication-free algorithm that employs the inherent algebraic properties of the AT. Low power has been achieved at the algorithmic level by replacing the multiplication with shifting operation, at the architecture level by using parallel computational units, and at the circuit level by using low power cells. The proposed architecture can be used as a computational kernel in object-based video processing. It is compatible with MPEG-4 and VRML standards. The architecture has been prototyped in 0.6 /spl mu/m CMOS technology with three layers of metal.