Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086)最新文献_第7页

Tighten the computation of worst-case execution-time by detecting feasible paths 通过检测可行路径，缩短了最坏情况下执行时间的计算

Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086) Pub Date : 2000-02-20 DOI: 10.1109/PCCC.2000.830347

H. Aljifri, A. Pons, M. Tapia

引用次数: 10

Self-similarity in a multi-stage queueing ATM switch fabric 多阶段排队ATM交换结构中的自相似性

Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086) Pub Date : 2000-02-20 DOI: 10.1109/PCCC.2000.830312

Adam Lange-Pearson

引用次数: 2

On the dynamic quality of service in wireless computing environments 无线计算环境下的动态服务质量研究

Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086) Pub Date : 2000-02-20 DOI: 10.1109/PCCC.2000.830322

C. Ben Ahmed, N. Boudriga, M. Obaidat

引用次数: 3

On fault location in networks by passive testing 基于被动测试的网络故障定位研究

Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086) Pub Date : 2000-02-20 DOI: 10.1109/PCCC.2000.830329

R.E. Miller, K. A. Arisha

引用次数: 37

Transport architecture for UMTS/IMT-2000 cellular networks UMTS/IMT-2000蜂窝网络的传输体系结构

Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086) Pub Date : 2000-02-20 DOI: 10.1109/PCCC.2000.830320

Barani Subbiah, Y. Raivio

引用次数: 3

Entity-centric scalable concurrency control for distributed interactive applications 用于分布式交互式应用程序的以实体为中心的可扩展并发控制

Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086) Pub Date : 2000-02-01 DOI: 10.1109/PCCC.2000.830361

Dongman Lee, Jeonghwa Yang, H. Youn, Chansu Yu, S. Hyun

引用次数: 11

Dynamic and adaptive cache prefetch policies 动态预取和自适应预取策略

Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086) Pub Date : 1900-01-01 DOI: 10.1109/PCCC.2000.830357

R. Oliver, P. Teller

{"title":"Dynamic and adaptive cache prefetch policies","authors":"R. Oliver, P. Teller","doi":"10.1109/PCCC.2000.830357","DOIUrl":"https://doi.org/10.1109/PCCC.2000.830357","url":null,"abstract":"This paper begins an exploration of the applicability of traditional prefetching policies in multiprocessor architectures. In particular, the effectiveness of prefetching policies as a function of both the quality of the prefetching and the consumption of processor to memory bandwidth is an issue of interest. Addressing this issue, the concept of a dynamic and adaptive cache (DAC), two new prefetch policies, and the design of an instruction DAC, called the DAC/sup 3/, which dynamically changes its prefetch policy at runtime, in response to process execution characteristics, are introduced. In addition, a detailed performance analysis of the DAC/sup 3/ and two new prefetch policies, which the DAC/sup 3/ uses, are presented; the performance of the DAC/sup 3/ is compared to that of the SSB prefetch instruction cache, which is based on Jouppi's sequential stream buffer design. This performance analysis is based on a new metric called CompositeCPI, which captures the usefulness of prefetches and their cost in terms of consumed memory bandwidth. The performance analysis indicates that, for the cache configurations and multiprogram workloads studied, the DAC/sup 3/ is superior to the SSB instruction prefetch cache.","PeriodicalId":387201,"journal":{"name":"Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134062646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Execution characteristics of multimedia applications on a Pentium II processor 多媒体应用程序在Pentium II处理器上的执行特性

Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086) Pub Date : 1900-01-01 DOI: 10.1109/PCCC.2000.830358

D. Talla, L. John

{"title":"Execution characteristics of multimedia applications on a Pentium II processor","authors":"D. Talla, L. John","doi":"10.1109/PCCC.2000.830358","DOIUrl":"https://doi.org/10.1109/PCCC.2000.830358","url":null,"abstract":"With the widespread use of 3D graphics, animation, speech recognition, and other media applications, general-purpose processors are increasingly spending their cycles on video and audio processing. However, the characteristics of media applications when executed on general purpose processors are not well understood. Such knowledge is extremely important in guiding the design of future microprocessors and development of media applications. In this paper we characterize the performance of multimedia applications on art Intel Pentium II processor based system. Six different commercial multimedia applications belonging to 3D graphics, streaming video or streaming audio categories are executed on an Intel Pentium II processor and performance is measured. Architectural data pertaining to utilization of various hardware resources on the chip are collected using on-chip performance monitoring counters. Multimedia applications are seen to have fewer branch instructions than SPECint benchmarks, however more than SPECfp benchmarks. Despite a regular control flow and more available parallelism, the average number of cycles taken to execute an instruction is seen to be higher than that of SPECint. In many aspects, media applications exhibit a behavior between that of SPECint and SPECfp.","PeriodicalId":387201,"journal":{"name":"Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125468799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Epidemic quorums for managing replicated data 用于管理复制数据的流行quorum

Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086) Pub Date : 1900-01-01 DOI: 10.1109/PCCC.2000.830306

J. Holliday, R. Steinke, D. Agrawal, A. El, AbbadiDepartment

引用次数: 32

Analyzing instruction prefetching techniques via a cache performance model: effectiveness and limitations 通过缓存性能模型分析指令预取技术:有效性和局限性

Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086) Pub Date : 1900-01-01 DOI: 10.1109/PCCC.2000.830356

G. Park, T. Han, Shin-Dug Kim

{"title":"Analyzing instruction prefetching techniques via a cache performance model: effectiveness and limitations","authors":"G. Park, T. Han, Shin-Dug Kim","doi":"10.1109/PCCC.2000.830356","DOIUrl":"https://doi.org/10.1109/PCCC.2000.830356","url":null,"abstract":"Instruction prefetching methods are analyzed using a cache performance model. Improvement in performance achieved by using an instruction prefetching method is classified into two factors: the number of cache misses reduced by prefetching and the average amount of miss penalty reduced by successful prefetches. Conventional instruction prefetching methods are analyzed based on these two factors. Results show that the amount of miss penalty reduced by successful prefetches, called prefetch efficiency, is more crucial in obtaining a significant improvement in performance than the number of cache misses reduced by a given prefetching method. The effectiveness and limitations of conventional methods used to increase prefetch efficiency are examined using the analytical model and simulation. The analysis reveals that any effective instruction prefetching technique should be designed by utilizing the architectural characteristics of the underlying memory system as an important fundamental direction to achieve significant performance improvement required for future high performance systems.","PeriodicalId":387201,"journal":{"name":"Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference (Cat. No.00CH37086)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130859722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0