Dynamic and adaptive cache prefetch policies

Abstract

This paper begins an exploration of the applicability of traditional prefetching policies in multiprocessor architectures. In particular, the effectiveness of prefetching policies as a function of both the quality of the prefetching and the consumption of processor to memory bandwidth is an issue of interest. Addressing this issue, the concept of a dynamic and adaptive cache (DAC), two new prefetch policies, and the design of an instruction DAC, called the DAC/sup 3/, which dynamically changes its prefetch policy at runtime, in response to process execution characteristics, are introduced. In addition, a detailed performance analysis of the DAC/sup 3/ and two new prefetch policies, which the DAC/sup 3/ uses, are presented; the performance of the DAC/sup 3/ is compared to that of the SSB prefetch instruction cache, which is based on Jouppi's sequential stream buffer design. This performance analysis is based on a new metric called CompositeCPI, which captures the usefulness of prefetches and their cost in terms of consumed memory bandwidth. The performance analysis indicates that, for the cache configurations and multiprogram workloads studied, the DAC/sup 3/ is superior to the SSB instruction prefetch cache.